PSD834F2-15J STMicroelectronics, PSD834F2-15J Datasheet - Page 20

• Manufacturer Part Number: PSD834F2-15J
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
Data Toggle. Checking the Toggle Flag (DQ6)
Bit is a method of determining whether a Program
or Erase cycle is in progress or has completed.
Figure 5 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Toggle Flag (DQ6) Bit of this location toggles each
time the MCU reads this location until the embed-
ded algorithm is complete. The MCU continues to
read this location, checking the Toggle Flag (DQ6)
Bit and monitoring the Error Flag (DQ5) Bit. When
the Toggle Flag (DQ6) Bit stops toggling (two con-
secutive READs yield the same value), and the Er-
ror Flag (DQ5) Bit remains '0,' the embedded
algorithm is complete. If the Error Flag (DQ5) Bit is
'1,' the MCU should test the Toggle Flag (DQ6) Bit
again, since the Toggle Flag (DQ6) Bit may have
changed simultaneously with the Error Flag (DQ5)
Bit (see Figure 5).
Figure 5. Data Toggle Flowchart
20/95
NO
DQ5 & DQ6
READ DQ6
TOGGLE
TOGGLE
START
READ
FAIL
DQ6
DQ5
DQ6
= 1
=
=
YES
YES
YES
NO
NO
PASS
AI01370B
The Error Flag (DQ5) Bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 5 still applies. the Toggle Flag
(DQ6) Bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) Bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. The MCU can read any location within the sec-
tor being erased to get the Toggle Flag (DQ6) Bit
and the Error Flag (DQ5) Bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass. The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first initiating two Unlock cycles. This is followed
by a third WRITE cycle containing the Unlock By-
pass code, 20h (as shown in Table 7).
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset Flash in-
struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.