MCIMX27VJP4A Freescale, MCIMX27VJP4A Datasheet - Page 86

• Manufacturer Part Number: MCIMX27VJP4A
• Manufacturer: Freescale

Specifications of MCIMX27VJP4A

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.3.11.2
Figure 47
parameters.
86
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•
•
•
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
Synchronous Internal Clock Operation
and
SS42
SS43
SS52
ID
SSI Receiver Timing with Internal Clock
Figure 48
AD1_TXFS (wl)
Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued)
AD1_TXFS (bl)
(Output)
(Output)
AD1_RXD
AD1_TXC
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
Loading
(Input)
(Output)
AD1_RXC
(Output)
Figure 47. SSI Receiver with Internal Clock Timing Diagram
show the SSI receiver timing with internal clock, and
SS48
SS2
SS7
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Parameter
SS47
SS1
SS11
SS9
SS20
SS51
SS5
SS50
SS4
10.0
Min
SS21
—
0
SS49
SS3
Max
Table 47
25
—
—
Freescale Semiconductor
SS13
lists the timing
Unit
pF
ns
ns