MCIMX27VJP4A Freescale, MCIMX27VJP4A Datasheet - Page 55

• Manufacturer Part Number: MCIMX27VJP4A
• Manufacturer: Freescale

Specifications of MCIMX27VJP4A

• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
1
2
3
4
5
Note:
The output SCLK transition time is tested with 25 pF drive.
T
T
T
T
wait
sclk
per
ipg
Num
t10
t11
t12
t13
ID
t1’
t2’
t3’
t5’
t6’
t7’
t1
t2
t3
t4
t5
t6
t7
t8
t9
= CSPI main clock IPG_CLOCK period
= CSPI reference baud rate clock period (PERCLK2)
= Wait time as per the Sample Period Control Register value.
= CSPI clock period
CSPI master SCLK cycle time
CSPI master SCLK high time
CSPI master SCLK low time
CSPI slave SCLK cycle time
CSPI slave SCLK high time
CSPI slave SCLK low time
CSPI SCLK transition time
SSn output pulse width
SSn input pulse width
SSn output asserted to first SCLK edge (SS output
setup time)
SSn input asserted to first SCLK edge (SS input
setup time)
CSPI master: Last SCLK edge to SSn deasserted
(SS output hold time)
CSPI slave: Last SCLK edge to SSn deasserted
(SS input hold time)
CSPI master: CSPI1_RDY low to SSn asserted
(CSPI1_RDY setup time)
CSPI master: SSn deasserted to CSPI1_RDY low
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Parameter Description
Table 23. CSPI Interface Timing Parameters
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Symbol
t
t
t
t
t
t
Sdatao
Hdatao
t
t
t
t
t
t
t
Sdatai
Hdatai
t
t
clkoH
Wsso
t
t
clkoL
Hsso
t
clkiH
t
Wssi
Ssso
clkiL
Hssi
Srdy
Hrdy
Sssi
clko
clki
pr
1
(t
t
2T
clkoL
t
clkoL
clkiL
T
t
clkiL
Minimum
sclk
T
per
ipg
45.12
22.65
22.47
3T
2T
2T
T
T
or t
or t
60.2
30.1
30.1
or t
2
2.6
+ 20 ns
30
or t
per
ipg
0
5
sclk
sclk
+ 0.5
+T
per
clkoH
clkiH
clkoH
5
4
clkiH
wait
) -
or
or
3
Maximum
5T
Electrical Characteristics
8.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-
per
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
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