MCIMX27VJP4A Freescale, MCIMX27VJP4A Datasheet - Page 12

• Manufacturer Part Number: MCIMX27VJP4A
• Manufacturer: Freescale

Specifications of MCIMX27VJP4A

• Lead Free Status / RoHS Status: Compliant

Functional Description and Application Information
Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial
interfaces, and the external ports connect to off-chip audio devices and serial interfaces of other processors.
A desired connectivity is achieved by configuring the appropriate internal and external ports.
The module includes full 6-wire SSI interfaces for asynchronous receive and transmit, as well as a
configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface. The AUDMUX allows
each host interface to be connected to any other host or peripheral interface in a point-to-point or
point-to-multipoint (network mode).
2.3.7
The Clock and Reset Module (CRM) generates clock and reset signals used throughout the
i.MX27/MX27L processor and for external peripherals. It also enables system software to control,
customize, or read the status of the following functions:
2.3.8
The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27/MX27L processors to
connect directly to external CMOS sensors and CCIR656 video source.
The capabilities of the CSI include the following:
12
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Chip ID
Multiplexing of I/O signals
I/O Driving Strength
I/O Pull Enable Control
Well-Bias Control
System boot mode selection
DPTC Control
Configurable interface logic to support popular CMOS sensors in the market
Support traditional sensor timing interface
Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and
NTSC input
8-bit input port for YCC, YUV, Bayer, or RGB data
32 × 32 FIFO storing image data supporting Core data read and DMA data burst transfer to system
memory
Full control of 8-bit and 16-bit data to 32-bit FIFO packing
Direct interface to eMMA-lt Pre-Processing block (PrP) - Not available on the i.MX27L
Single interrupt source to interrupt controller from maskable sensor interrupt sources: Start of
Frame, End of Frame, Change of Field, FIFO full
Configurable master clock frequency output to sensor
Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27/MX27L
processor or by external clock source.
Clock and Reset Module (CRM)
CMOS Sensor Interface (CSI)
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Freescale Semiconductor