MCIMX27VJP4A Freescale, MCIMX27VJP4A Datasheet - Page 57

• Manufacturer Part Number: MCIMX27VJP4A
• Manufacturer: Freescale

Specifications of MCIMX27VJP4A

• Lead Free Status / RoHS Status: Compliant

4.3.2
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.3.2.1
The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 17
Freescale Semiconductor
T
T
T
T
min_assert
max_req_assert
max_read
max_write
M1
M2
M3
Parameter
FEC_RXD[3:0] (inputs)
ID
FEC_RX_CLK (input)
shows the MII receive signal timings, and
Fast Ethernet Controller (FEC)
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse width high
FEC_RX_ER
FEC_RX_DV
MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER,
and FEC_RX_CLK)
Minimum assertion time of External Grant signal
Maximum External Request assertion time after
assertion of Grant signal
Maximum External Request assertion time after
first read completion
Maximum External Request assertion time after
first write completion
Description
Table 25. MII Receive Signal Timing Parameters
Figure 17. MII Receive Signal Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Table 24. DMAC Timing Parameters
Parameter
M1
1
M2
M3
Table 25
9hclk–20.66
8hclk–6.21
3hclk–5.87
8hclk+8.6
WCS
lists the timing parameters.
3.0 V
8hclk+2.74
8hclk–0.77
3hclk–8.83
9hclk–6.7
BCS
M4
35%
Min
5
5
65%
Max
9hclk–17.96 9hclk–8.16
—
—
8hclk+7.17
8hclk–5.84
3hclk–15.9
WCS
FEC_RX_CLK period
Electrical Characteristics
1.8 V
8hclk+3.25
8hclk–0.66
3hclkv91.2
Unit
ns
ns
BCS
Unit
ns
ns
ns
ns
57