M393T5750CZ3-CD5 Samsung Semiconductor, M393T5750CZ3-CD5 Datasheet - Page 25

• Manufacturer Part Number: M393T5750CZ3-CD5
• Manufacturer: Samsung Semiconductor

Specifications of M393T5750CZ3-CD5

• Lead Free Status / RoHS Status: Compliant

RDIMM
15.0 240 Pin DDR2 Registered DIMM Clock Topology
Note :
CK0
CK0
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
120 ohms
C
120 ohms
IN
Feedback In
0ns (nominal)
Feedback Out
PLL
25 of 25
OUTN
OUT1
DDR2 SDRAM
DDR2 SDRAM
Reg.A
Reg.B
C
DDR2 SDRAM
Rev. 1.8 May 2007
120 ohms
120 ohms