M393T5750CZ3-CD5 Samsung Semiconductor, M393T5750CZ3-CD5 Datasheet - Page 21

• Manufacturer Part Number: M393T5750CZ3-CD5
• Manufacturer: Samsung Semiconductor

Specifications of M393T5750CZ3-CD5

• Lead Free Status / RoHS Status: Compliant

RDIMM
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Parameter
tXARD
tXARDS
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
Symbol
tAC(min)+
tAC(min)+
tAC(min)
tAC(min)
tIS+tCK
8 - AL
min
+tIH
2.5
3
2
2
2
3
8
0
DDR2-800
2
tAC(max)
tAC(max)
tAC(max)
tAC(max)
2.5tCK +
2tCK +
max
+ 0.7
+ 0.6
2.5
+1
+1
12
2
x
21 of 25
tAC(min)+
tAC(min)+
tAC(min)
tAC(min)
tIS+tCK
7 - AL
min
+tIH
2.5
3
2
2
2
3
8
0
DDR2-667
2
2tCK+tAC
2.5tCK+tA
C(max)+1
tAC(max)
tAC(max)
(max)+1
max
+ 0.6
+0.7
2.5
12
2
x
tAC(min)+
tAC(min)+
tAC(min)
tIS+tCK
tAC(min)
6 - AL
min
+tIH
2.5
3
2
2
2
3
8
0
2
DDR2-533
2tCK+tAC
tAC(max)
tAC(max)+
tAC(max)
(max)+1
2.5tCK+
max
2.5
+1
0.6
+1
12
2
x
tAC(min)+
tAC(min)+
tAC(min)
tAC(min)
tIS+tCK
6 - AL
min
+tIH
2.5
3
2
2
2
3
8
0
2
DDR2-400
DDR2 SDRAM
Rev. 1.8 May 2007
2tCK+tAC
tAC(max)
tAC(max)
tAC(max)+
(max)+1
2.5tCK+
max
2.5
0.6
+1
+1
12
2
x
tCK
Units
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
Notes