MT45V256KW16PEGA-70 WT Micron Technology Inc, MT45V256KW16PEGA-70 WT Datasheet - Page 14

• Manufacturer Part Number: MT45V256KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V256KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Configuration Register Operation
Figure 9:
Access Using ZZ#
Figure 10:
PDF: 09005aef832450a3/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN
CR[7]
Configuration Register Bit Mapping
Load Configuration Register Operation Using ZZ#
All must be set to "0"
0
1
Notes:
Reserved
Page mode enabled
Page Mode Enable/Disable
Page mode disabled (default)
A[17:8]
17–8
The configuration register (CR) defines how the PSRAM device performs a transparent
self refresh. Altering the refresh parameters can dramatically reduce current consump-
tion during standby mode. Page mode control is embedded in the CR. This register can
be updated any time the device is operating in a standby state. The control bits used in
the CR are shown in Figure 9. At power-up, the CR is set to 0010h.
1. Use of other settings will result in full-array refresh coverage.
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-
to-LOW transition (see Figure 10). The values placed on addresses A[17:0] are latched
into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t
Care.” Access using ZZ# is WRITE only.
Address
WE#
CE#
ZZ#
Page
A7
t < 500ns
7
Setting is ignored
CR[4]
(default 00b)
0
1
Ignored
A6
4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16
6
Sleep Mode
DPD enabled
PAR enabled (default)
A5
5
Valid address
Sleep
A4
4
Must be set to "0"
14
Reserved
A3
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CR[2]
A2
Configuration Register Operation
0
1
2
CR[1] CR[0]
0
0
PAR
A1
1
1
0
0
PAR Coverage
Full array (default)
None of array
A0
0
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