MT45V256KW16PEGA-70 WT Micron Technology Inc, MT45V256KW16PEGA-70 WT Datasheet - Page 12

• Manufacturer Part Number: MT45V256KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V256KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Low-Power Operation
Standby Mode Operation
Partial-Array Refresh
PDF: 09005aef832450a3/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM REFRESH operation on the full array. Standby operation occurs
when CE# and ZZ# are HIGH.
The device enters a reduced-power state upon completion of READ and WRITE opera-
tions when the address and control inputs remain static for an extended period of time.
This mode continues until a change occurs to the address or control inputs.
Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory
array. This feature enables the system to reduce refresh current by only refreshing that
part of the memory array that is absolutely necessary. The refresh options are “full array”
and “none of the array.” Data stored in addresses not receiving refresh will become
corrupted. READ and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1).
PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10µs.
Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immedi-
ately available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software-access sequence (see “Software
Access to the Configuration Register” on page 15). Using this method, PAR is enabled
immediately upon setting CR[4] to “1.” However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, even though ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up (see Figure 8 on page 13).
4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2007 Micron Technology, Inc. All rights reserved.