MT47H128M16RT-25E:C Micron Technology Inc, MT47H128M16RT-25E:C Datasheet - Page 71

• Manufacturer Part Number: MT47H128M16RT-25E:C
• Description: DRAM Chip DDR2 SDRAM 2G-Bit 128Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr
• Series: -r

Specifications of MT47H128M16RT-25E:C

• Package: 84FBGA
• Density: 2 Gb
• Address Bus Width: 17 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 800 MHz
• Maximum Random Access Time: 0.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (128M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Compliant

Commands
Truth Tables
Table 37: Truth Table – DDR2 Commands
Notes: 1–3 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Function
LOAD MODE
REFRESH
SELF REFRESH entry
SELF REFRESH exit
Single bank
PRECHARGE
All banks PRECHARGE
Bank ACTIVATE
WRITE
WRITE with auto
precharge
READ
READ with auto
precharge
NO OPERATION
Device DESELECT
Power-down entry
Power-down exit
Notes:
Previous
Cycle
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at
2. The state of ODT does not affect the states described in this table. The ODT function is
3. “X” means “H or L” (but a defined logic level) for valid I
4. BA2 is only applicable for densities ≥1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larg-
CKE
the rising edge of the clock.
not available during self refresh. See ODT Timing (page 128) for details.
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.
Current
Cycle
H
H
H
H
H
H
H
H
H
H
X
X
H
L
L
CS#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS#
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
71
X
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
L
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WE#
H
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
2Gb: x4, x8, x16 DDR2 SDRAM
BA2–
BA0
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
An–A11
Column
Column
Column
Column
address
address
address
address
DD
X
X
X
X
X
X
X
X
X
measurements.
© 2006 Micron Technology, Inc. All rights reserved.
Row address
OP code
A10
X
X
X
H
H
H
X
X
X
X
L
L
L
Column
Column
Column
Column
address
address
address
address
Commands
A9–A0 Notes
X
X
X
X
X
X
X
X
X
4, 5, 6,
4, 5, 6,
4, 5, 6,
4, 5, 6,
4, 6
4, 7
6
4
8
8
8
8
9
9