MT28C6428P20FM-80 BET Micron Technology Inc, MT28C6428P20FM-80 BET Datasheet - Page 12

• Manufacturer Part Number: MT28C6428P20FM-80 BET
• Manufacturer: Micron Technology Inc

Specifications of MT28C6428P20FM-80 BET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02
CODE DEVICE MODE
10h
20h
40h
50h
60h
70h
90h
98h
B0h
C0h
APA
Erase Setup
Program Setup
Clear Status
Register
Protection
Configuration
Setup
Set Read
Configuration
Register
Read Status
Register
Read Protection
Configuration
Read Query
Program Suspend
Erase Suspend
Check Block
Erase Suspend
Program Device
Protection Register
Lock Device
Protection Register
BUS CYCLE
First
First
First
First
First
First
First
First
First
First
First
First
First
First
Command Descriptions
(continued on the next page)
A two-cycle command: The first cycle prepares for a PROGRAM
The WSM can set the program status (SR4), and erase status (SR5) bits
Puts the device into the read protection configuration mode so that
has been successfully suspended by setting either the program
“1” (ready). The WSM continues to idle in the suspend state,
regardless of the state of all input control pins except F_RP#, which
Writes a specific code into the device protection register.
Prepares for an accelerated program operation.
Prepares the CSM for the ERASE command. If the next command is
not a CHECK BLOCK ERASE OR ERASE CONFIRM command, the
command will be ignored, and the device will go to read status
mode and wait for another command.
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
this command clears those bits to “0.”
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
DOWN, the command will be ignored, and the device will go to read
status mode.
Puts the device into the set read configuration mode so that it will be
possible to set the option bits related to burst read mode.
Places the device into read status register mode. Reading the device
outputs the contents of the status register for the addressed bank.
The device automatically enters this mode for the addressed bank
after a PROGRAM or ERASE operation has been initiated.
reading the device outputs the manufacturer/device codes or block
lock status.
Puts the device into the read query mode so that reading the device
outputs common Flash interface information.
Suspends the currently executing PROGRAM/ERASE/CHECK BLOCK
ERASE operation. The status register indicates when the operation
suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a
immediately shuts down the WSM and the remainder of the chip if
F_RP# is driven to V
Locks the device protection register; data can no longer be changed.
in the status register to “1,” but it cannot clear them to “0.” Issuing
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
Table 5
12
512K x 16 SRAM COMBO MEMORY
IL
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.