AD9937KCP Analog Devices Inc, AD9937KCP Datasheet - Page 9

• Manufacturer Part Number: AD9937KCP
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCP

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

Addr
0
1
2
3
4
5
6
7
REV. 0
Bit
Breakdown Width
(23:0)
0
(23:1)
(1:0)
2
(23:3)
(7:0)
8
9
10
11
12
13
14
(16:15)
17
18
(23:19)
0
1
2
3
4
5
(23:6)
(5:0)
(11:6)
(17:12)
(19:18)
20
21
22
23
(5:0)
(11:6)
(17:12)
(23:18)
(2:0)
(5:3)
(8:6)
(23:9)
(23:1)
Bit
24
1
23
2
1
21
8
1
1
1
1
1
1
1
2
1
1
5
1
1
1
1
1
1
18
6
6
6
2
1
1
1
1
6
6
6
6
3
3
3
15
23
Default
0
0
0
0
0x80
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0x00
0x24
0x00
0x00
0
1
0
–
0x00
0x20
0x00
0x10
4
4
4
Register
Name
SW_RESET
OUTCONT_REG
Unused
AFE_STBY
DIG_STBY
Unused
REFBLACK
BC_EN
TESTMODE
TESTMODE
PBLK_LEVEL
TRISTATEOUT
RETIMEOUT_BAR 0 = Retime Data Outputs, 1 = Do Not Retime Data Outputs.
GRAY_ENCODE
TESTMODE
TESTMODE
TESTMODE
Unused
VCKM_DIVIDE
H1BLKRETIME
LM_INVERT
TGOFD_INVERT
VDHD_INVERT
MASTER
Unused
SHDLOC
SHPLOC
DOUTPHASE
DOUT_DELAY
VCLKMASK
VCLK_INVERT
DTEST
Unused
H1POSLOC
H1NEGLOC
RSPOSLOC
RSNEGLOC
H1DRV
H2DRV
RSDRV
Unused
Unused
Table I. Control Register Map
–9–
Software Reset = 000000 (Reset All Registers to Default).
Internal OUTCONT Signal Control (0 = Digital Outputs held
AFE Standby (0 = Full Standby, 1 = Normal Operation,
Digital Standby (0 = Full Standby, 1 = Normal Operation).
Black Clamp Level.
This register should always be set to 0.
This register should always be set to 0.
0 = Blank to 0, 1 = Blank to Clamp Level (REFBLACK).
1 = Gray Encode ADC Outputs.
This register should always be set to 0.
This register should always be set to 0.
This register should always be set to 1.
VCKM Input Clock Divider (0 = VCKM, 1 = VCKM/2).
Retimes the H1 HBLK to Internal Clock.
LM Inversion Control (1 = Invert Programmed LM).
TG and OFD Inversion Control (1 = Invert Programmed TG
VD and HD Inversion Control (1 = Invert Programmed VD
SHD Sample Location.
SHP Sample Location.
Data Output [9:0] and VCLK Phase Adjustment.
VCLK Masking Control (1 = Mask).
1 = Invert VCLK.
H1 Positive Edge Location.
H1 Negative Edge Location.
RS Positive Edge Location.
RS Negative Edge Location.
H2A/B Drive Strength (see H1DRV).
RS Drive Strength (see H1DRV).
Function
at fixed dc level, 1 = Normal Operation).
2/3 = Reference Standby).
1 = Black Clamp Enable.
0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated.
and ODF).
and HD; Note that Internal VD/HD Are HI Active).
Operating Mode (0 = Slave Mode, 1 = Master Mode).
Data Output Clock Selection (0 = No Delay, 1 = ~4 ns, 2 = ~8 ns,
3 = ~12 ns).
1 = Internal Digital Signal Test Mode.
H1A/B/C/D Drive Strength (0 = OFF, 1 = 1.75 mA, 2 = 3.5 mA,
3 = 5.25 mA, 4 = 7 mA, 5 = 8.75 mA, 6 = 10.5 mA, 7 = 12.25 mA).
AD9937