AD9937KCP Analog Devices Inc, AD9937KCP Datasheet - Page 39

• Manufacturer Part Number: AD9937KCP
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCP

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

POWER-UP FOR MASTER MODE
When the AD9937 is powered up, the following sequence is
recommended. (Refer to Figure 37 for each step.)
1. Turn on power supplies for AD9937.
2. The internal power-on auto-reset circuit will deassert
3. The VCKM clock can be applied as soon as VDD settles.
4. Reset the internal AD9937 registers: write a 0x000000 to
5. Write a 1 to the DIG_STBY and AFE_STBY registers
6. Program all control, system, and mode registers.
7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put
REV. 0
CONTROLLED)
AUTO-RESET
(LO-ACTIVE)
1.0 ms after VDD settles. (All internal registers are reset to
the default values.)
the SW_RESET register (addr 0x00). This will set all inter-
nal register values to their default values. (This step is optional
because the internal power-on reset circuit is applied at
power-up.)
(addr 0x02). This will put the digital and analog circuits into
the normal operating mode.
the digital outputs into the normal operating mode. The inter-
nal OUTCONT will be asserted high on the rising edge of the
32nd SCK clock when writing to the OUTCONT_REG.
POWER-ON
(REGISTER
INTERNAL
OUTCONT
(OUTPUT)
(OUTPUT)
OUTPUTS
DIGITAL
WRITES
(INPUT)
SERIAL
VCKM
VCLK
VDD
HD
VD
NOTES
1
2
3
1
THE INTERNAL POWER-ON AUTO RESET TIME
IT TAKES 500 s FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED.
IT TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
2
t
PWR
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
RS, H2(A, B), LM
1
4
5
6
Figure 37. Recommended Power-Up Sequence
t
SETTINGS
t
PWR
2
= 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.
7
–39–
t
DELAY
1H
ODD FIELD
3
Output
V1A/B
V2
V3A/B
V4
TG1A
TG1B
TG3A
TG3B
OFD
H1(A–D)
H2(A, B)
LM
RS
1V
Table XVIII. Start-Up Polarities
(While OUTCONT = LO)
EVEN FIELD
OUTCONT = LO
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
AD9937
ODD FIELD