AD9937KCP Analog Devices Inc, AD9937KCP Datasheet - Page 35

• Manufacturer Part Number: AD9937KCP
• Manufacturer: Analog Devices Inc

Specifications of AD9937KCP

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Not Compliant

VERTICAL TIMING GENERATION
The AD9937 provides a very flexible solution for generating
vertical CCD timing, and can support multiple CCDs and differ-
ent system architectures. The 4-phase vertical transfer clocks
V1–V4 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9937 allows these outputs
to be individually programmed into different pulse patterns.
Vertical sequence control registers then organize the individual
vertical pulses into the desired CCD vertical timing arrangement.
The AD9937 can preprogram three unique sets of vertical transfer
pulses known as VTP0, VTP1, and VTP2. Each VTP set consists
of the four vertical clocks (V1A/B, V2, V3A/B, and V4), as shown
in Figure 32. Once preprogrammed, any one of the three unique
VTP sets can then be selected to be output in any one of the
five CCD regions by using the VTPPATSELx (x = 0, 1, 2, 3, 4)
registers. The VTP_Reg(1–9) registers listed in Table II are used
for generating the VTP pulse sets.
Figure 32 shows an example of programming one VTPx (x = 0, 1, 2)
pulse set. Once a VTP pulse set has been configured, multiple
repetitions of this set can be repeated to create an entire VTP
sequence. This is accomplished by using the VTPREPn
(n = 0, 1, 2, 3, 4) registers where n represents the five CCD regions.
An example of repeating a VTP set is shown in Figure 33.
Register Name*
SCP1
SCP2
SCP3
SCP4
*There is no SCP0 register. The SCP0 position is always fixed at Line 0.
REV. 0
Figure 30. Example of Vertical HMASK Masking with HDLASTLEN > HDLEN with HMASTKSTART = 0 and HMASKSTOP = 1560
H1
H2
131
HBLKTOG2
HBLK
132
133
HDLEN
134
Length
(Bits)
8
8
8
8
135
154
HDLASTLEN
155
Table XVII. Sequence Change Positions Registers
Register
Type
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
156
H1TOG34POL
HMASK
233
0
234
–35–
Range
0–255 Line Positions
0–255 Line Positions
0–255 Line Positions
0–255 Line Positions
CCD REGIONS
Up to five unique CCD regions can be preprogrammed using the
sequence change position registers as described in Table XVII.
The SCPx (x = 0, 1, 2, 3, 4) registers determine when the set-
tings in Mode_Reg(15–19) are active. For example, the SCP1
register activates the registers at Mode_Reg(16) for CCD region 1.
Note that SCP0 is not programmable. The SCP0 position always
starts at Line 0, as shown in Figure 31.
1
2
REGISTERS LOCATED AT MODE_REG(15)
REGISTERS LOCATED AT MODE_REG(17)
REGISTERS LOCATED AT MODE_REG(19)
REGISTERS LOCATED AT MODE_REG(16)
REGISTERS LOCATED AT MODE_REG(18)
VERTICAL HMASK
Figure 31. Sequence Change Positions
OPERATING IN CCD REGION 0
OPERATING IN CCD REGION 4
OPERATING IN CCD REGION 1
OPERATING IN CCD REGION 2
OPERATING IN CCD REGION 3
ARE ACTIVE WHILE
ARE ACTIVE WHILE
ARE ACTIVE WHILE
ARE ACTIVE WHILE
ARE ACTIVE WHILE
CCD REGION 0
CCD REGION 1
CCD REGION 3
CCD REGION 4
CCD REGION 2
HBLKTOG1
Description
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
1559
H1MASKPOL
1560
0
HMASK
1
H1TOG12POL
SCP0
(FIXED AT LINE 0)
SCP1 [7:0]
SCP2 [7:0]
SCP3 [7:0]
SCP4 [7:0]
AD9937
2
HBLK
3
4