AD9937KCP Analog Devices Inc, AD9937KCP Datasheet
AD9937KCP
Specifications of AD9937KCP
Related parts for AD9937KCP
AD9937KCP Summary of contents
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FEATURES 12 MSPS Correlated Double Sampler (CDS) 10-Bit 12 MHz A/D Converter No Missing Codes Guaranteed Variable Gain Amplifier (VGA) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with ...
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AD9937 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD9937–SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RSVDD (RS Driver) HVDD1 (H1A, H2A, and H1C Drivers) HVDD2 (H1B, H2B, and H1D Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER ...
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AD9937 ANALOG SPECIFICATIONS Parameter CDS Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Code 0) Max Gain ...
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... V +3.9 V +3.9 V Model +3.9 V +3.9 V AD9937KCP RSVDD + 0.3 V HVDD + 0.3 V DVDD + 0.3 V DVDD + 0.3 V AD9937KCPRL –25°C to +85°C DVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V °C 150 °C 350 –5– MHz, unless otherwise noted.) CLI Min Typ Max 83.33 41.67 ...
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AD9937 CONNECT Pin 2 No. Mnemonic Type Description Connect Connect Data Output Data Output Data Output Data ...
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TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates ...
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AD9937–Typical Performance Characteristics 160 150 V = 3.3V DD 140 130 V = 3.0V DD 120 V = 2.7V DD 110 100 8 10 SAMPLE RATE – MHz TPC 1. Power vs. Sample Rate 0.50 0.25 0 –0.25 –0.50 0 ...
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Bit Bit Addr Breakdown Width Default 0 (23: (23: (1: (23: (7:0) 8 0x80 ...
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AD9937 Bit Bit Addr Breakdown Width Default (23: (4:1) 4 0x9 (23: (11:1) 11 0x7FF (23:13 (11:0) 12 4095 (23:12) 12 ...
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Table II. VTP Sequence System Register Map (Addr 0x14) (continued) Bit Bit Addr Breakdown Width VTP_Reg(6) (8:0) 9 (17:9) 9 (26:18) 9 (31:27) 5 VTP_Reg(7) (8:0) 9 (17:9) 9 (26:18 ...
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AD9937 Bit Bit Addr Breakdown Width HLM_Reg(0) (11:0) 12 (23:12) 12 (31:24) 8 HLM_Reg( (31:6) 26 HLM_Reg(2) (5:0) 6 (11:6) 6 (17:12) 6 (31:18) 14 HLM_Reg(3) (5:0) 6 ...
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Bit Bit Addr Breakdown Width Shut_Reg(0) (11:0) 12 (23:12) 12 (31:24) 8 Shut_Reg(1) (11:0) 12 (23:12) 12 (31:24) 8 Shut_Reg(2) (11:0) 12 (23:12) 12 (31:24) 8 Shut_Reg(3) (11:0) 12 (23:12) 12 (31:24) 8 Shut_Reg(4) (11:0) 12 (23:12) 12 (31:24) 8 ...
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AD9937 Bit Bit Addr Breakdown Width Mode_Reg(0) (11:0) 12 (23:12) 12 (31:24) 8 Mode_Reg(1) (6: (12: (31:14) 18 Mode_Reg(2) (11:0) 12 (23:12) 12 (31:24) 8 Mode_Reg(3) (11:0) 12 (23:12) 12 (31:24) 8 ...
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Bit Bit Addr Breakdown Width Mode_Reg(14) (7:0) 8 (15:8) 8 (23:16) 8 (31:24) 8 Mode_Reg(15) (11:0) 12 (13:12) 2 (16:14 (19:18 (31:22) 10 Mode_Reg(16) (11:0) 12 (13:12) 2 (16:14 ...
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AD9937 Bit Bit Addr Breakdown Width Mode_Reg(0) (11:0) 12 (23:12) 12 (31:24) 8 Mode_Reg(1) (6: (12: (31:14) 18 Mode_Reg(2) (11:0) 12 (23:12) 12 (31:24) 8 Mode_Reg(3) (11:0) 12 (23:12) 12 (31:24) 8 ...
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Bit Bit Addr Breakdown Width Mode_Reg(14) (7:0) 8 (15:8) 8 (23:16) 8 (31:24) 8 Mode_Reg(15) (11:0) 12 (13:12) 2 (16:14 (19:18 (31:22) 10 Mode_Reg(16) (11:0) 12 (13:12) 2 (16:14 ...
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AD9937 SERIAL INTERFACE TIMING All of the internal registers of the AD9937 are accessed through a 3-wire serial interface. The 3-wire interface consists of a clock (SCK), serial load (SLD), and serial data (SDA). The AD9937 has three different register ...
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REG ADDRESS [7:0] SDA 8 BIT ADDRESS SCK SLD 1. ALL SLD PULSES ARE IGNORED UNTIL THE LAST BIT OF THE LAST DATA N WORD IS CLOCKED IN. 2. THE SLD PULSE MUST BE ASSERTED HIGH WHEN ALL SDA ...
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AD9937 SYSTEM OVERVIEW Figure 8 shows the typical system block diagram for the AD9937. The CCD output is processed by the AD9937’s AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information ...
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ANALOG FRONT END DESCRIPTION AND OPERATION The AD9937 AFE signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. DC Restore To reduce the large ...
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AD9937 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9937 generates flexible high speed timing signals using the precision timing core. This core is the foundation for gener- ating the timing used for both the CCD and the AFE: the reset ...
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Table VIII. RS, H1, SHP, SHD, and DOUTPHASE Timing Parameters Bit Width Register Name* (Bits) RSPOSLOC 6 RSNEGLOC 6 H1POSLOC 6 H1NEGLOC 6 SHPLOC 6 SHDLOC 6 DOUTPHASE 6 *The 2 MSB bits are used to select the quadrant. Table ...
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AD9937 P[0] POSITION PIXEL PERIOD RSr[0] RS Hr[0] H1 CDS (INTERNAL) CCD SIGNAL Figure 14. High Speed Clock Default and Programmable Locations t RISE H1 H2 P[0] PIXEL PERIOD VCLK t OD DOUT 1. DOUTPHASE REGISTER (ADDR 0x05) CAN BE ...
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MASTER AND SLAVE MODE OPERATION The AD9937 defaults at power up into slave mode operation. During slave mode operation, the VD and HD pins are config- ured as inputs for external VD and HD signals. The AD9937 can be configured ...
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AD9937 11-BIT 000 VD COUNTER 12-BIT HD COUNTER * HDLENx OPTIONAL SECOND HD PULSE PER LINE * REPRESENTING CCD REGIONS PROGRAMMABLE CLOCK POSITIONS 1. VDHD_INVERT ...
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HD COUNTER PBLK 1 PROGRAMMABLE CLOCK POSITIONS 1. PBLKTOG1 (PROGRAMMABLE AT MODE_REG(9)) 2. PBLKTOG2 (PROGRAMMABLE AT MODE_REG(9)) 3. PBLKTOG3 (PROGRAMMABLE AT MODE_REG(10)) 4. PBLKTOG4 (PROGRAMMABLE AT MODE_REG(10)) PBLKTOG1 = 500 PBLK 1. PBLKTOG1 = 500 2. PBLKTOG2 = 785 ...
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AD9937 11-BIT 000 VD COUNTER 12-BIT HD COUNTER VD HD PBLK Figure 21. Example with PBLKSTOP = PBLKSTART = 2048 Controlling CLPOB Clamp Pulse Timing Up to two individual CLPOB pulses can be programmed per line using the CLPOBTOGx (x ...
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VD HD CLPOB Vertical Sensor Transfer Gate Timing The vertical transfer sensor gate (TG) pulses are used to trans- fer the pixel charges from the light-sensitive image area into the light-shielded vertical registers. When a mechanical shutter is not being ...
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AD9937 Length Register Register Name (Bits) Type OFDEN 1 Control 0x10 OFDNUM 11 Control 0x10 OFDHPTOG1 12 Control 0x11 OFDHPTOG2 12 Control 0x11 OFDTOG1_0 12 Shut_Reg(3) OFDTOG2_0 12 Shut_Reg(3) OFDTOG1_1 12 Shut_Reg(4) OFDTOG2_1 12 Shut_Reg(4) OFDPATSEL 1 Mode_Reg(1) 11-BIT 000 ...
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Controlling LM Pulse Timing The AD9937 provides an LM output pulse that is fully program- mable by using the registers in Table XV. Two unique sets of LM pulses can be preprogrammed using the LMLENx, LMTOG1_x, and LMTOG2_x (x = ...
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AD9937 12-BIT HD COUNTER 1 LMLENx 8-BIT LM COUNTER LMx LM PULSE SET 1 LMSTART0 NOTES (TWO UNIQUE SETS OF LM OUTPUTS CAN BE PROGRAMMED ...
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MASKING H1 AND H2 OUTPUTS The H1 and H2 outputs can be masked during the horizontal and vertical transfers as shown in Figures 29 and 30. Horizontal Masking The H1 clocks are masked with the polarity set by the H1MASKPOL ...
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AD9937 LMSTART0 HBLKTOG1 SPHSTARTx H1A 2 3 HBLKTOG2 PROGRAMMING NOTES 1. THERE ARE TWO SPHSTART REGISTERS. THEY ARE SPHSTART0 AND SPHSTART1. SPHSTART0 IS USED WHEN THE LM0 PULSE IS SELECTED BY SETTING LMPATSEL = 0. SPHSTART1 IS USED WHEN THE ...
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HBLK 131 132 133 134 135 154 155 H1 H2 HBLKTOG2 HDLEN HDLASTLEN Figure 30. Example of Vertical HMASK Masking with HDLASTLEN > HDLEN with HMASTKSTART = 0 and HMASKSTOP = 1560 VERTICAL TIMING GENERATION The AD9937 provides a very ...
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AD9937 12-BIT HD COUNTER V1A V3A VTPLEN_x* PROGRAMMING NOTES *( THE x REPRESENTS THE THREE SEPARATE REGISTERS FOR VTP0, VTP1, AND VTP2 SETS. THIS ALSO APPLIES ...
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HD COUNTER VTPLEN_0 V1A/B V2 V3A/B V4 VTP0 Figure 34. Example of Three Preprogrammed VTP Pulses SCP0 (FIXED AT LINE 0) 11-BIT 000 VD COUNTER 12-BIT HD COUNTER VD HD V1A/B V2 V3A/B V4 VTPPATSEL0 = 1 VREP0 = ...
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AD9937 SCP0 (FIXED AT LINE 0) 11-BIT 000 VD COUNTER 12-BIT HD COUNTER VD HD V1A/B V2 V3A/B V4 VTPPATSEL0 = 1 VREP0 = 1 Figure 36. Example of VTP Pulse Sequence with VREP = 2 in CCD Region 1 ...
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VDD 1 (INPUT PWR INTERNAL POWER-ON 2 AUTO-RESET (LO-ACTIVE) VCKM 4 5 SERIAL WRITES OUTCONT (REGISTER CONTROLLED) VD (OUTPUT) HD (OUTPUT) V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B, OFD, H1( DIGITAL OUTPUTS RS, H2(A, ...
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AD9937 VDD (INPUT) 3 VCKM 1 2 SERIAL WRITES OUTCONT (INTERNAL SIGNAL) VD (OUTPUT) HD (OUTPUT) DIGITAL OUTPUTS AFE_STBY (REGISTER) DIG_STBY (REGISTER) *IT TAKES 4 VCKM CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA ...
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POWER-DOWN SEQUENCE The following sequence is recommended when AD9937 is being powered down. (Refer to Figure 39 for each step.) 1. Write the OUTCONT_REG register (addr 0x01). VDD (INPUT) VCKM SERIAL WRITES OUTCONT (INTERNAL) VD ODD FIELD ...
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AD9937 CIRCUIT LAYOUT INFORMATION The AD9937 typical circuit connection is shown in Figure 41. The PCB layout is critical in achieving good image quality from the AD9937 product. All of the supply pins, particularly the AVDD, DVDD, TCVDD, RSVDD, HVDD1, ...
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Figures 42 and 43 show the recommended AD9937 supply group- ing. Figure 42 shows how the supplies should be tied together when there are only two available supply sources, whereas Figure 43 shows how the supplies can be tied together ...
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AD9937 BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.85 0.80 SEATING PLANE OUTLINE DIMENSIONS 56-Lead Lead Frame Chip Scale Package [LFCSP] (CP-56) Dimensions shown in millimeters 8.00 0.60 MAX 0.60 MAX 43 42 7.75 TOP BSC SQ VIEW 0.50 ...