SAA7118EEB-T NXP Semiconductors, SAA7118EEB-T Datasheet - Page 167

• Manufacturer Part Number: SAA7118EEB-T
• Description: Video ICs COMPONENT VID DECODER W/COMB F
• Manufacturer: NXP Semiconductors
• Type: Multi-Standard Video Decoderr

Specifications of SAA7118EEB-T

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-700
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Not Compliant
• Other names: SAA7118E/V1,518

NXP Semiconductors
SAA7118_7
Product data sheet
19.4 Issue 4: Erase condition for interrupt pin INT_A
19.5 Issue 5: Odd/even detection might become unreliable with signals
Background (how it should work):
The status flags are grouped into four 8-bit registers. The interrupt flag is to be cleared on
a read access to a status register, comprising the event that caused the interrupt.
This implies that it would be sufficient to clear the interrupt by reading only those registers
which have been enabled by their corresponding masks.
Anomaly description:
Three of the four register addresses for clearing the interrupt flag are wrong;
see
Table 151. Status bytes
Impact:
Output pin INT_A cannot be cleared by reading the corresponding addresses in three of
four cases.
Workaround:
To clear the interrupt flag, an additional read cycle to the implemented addresses is
required, e.g. to read register 1Eh and clear interrupt flag, read register 1Eh and
register 0Eh.
from video tape recorders
Background (how it should work):
The odd/even detection is a flag, available on a pin, to indicate the interlace of a video
signal; this should be independent of the type of input signal.
Anomaly description:
If a signal originated from a VTR suffers from phase errors greater than 16 s, the
odd/even detection might be set onto a wrong phase, thus interrupting the actual odd/even
sequence of the input signal.
Impact:
If the generated odd/even flag is being used in a succeeding signal processing, this
processing could eventually be upset due to incorrect detection.
Address to be read
Correct
1Eh
1Fh
60h
8Fh
Table
151.
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
Implemented
0Eh (incorrect)
0Fh (incorrect)
5Fh (incorrect)
8Fh (correct)
SAA7118
© NXP B.V. 2008. All rights reserved.
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