SAA7118EEB-T NXP Semiconductors, SAA7118EEB-T Datasheet - Page 141
SAA7118EEB-T
Manufacturer Part Number
SAA7118EEB-T
Description
Video ICs COMPONENT VID DECODER W/COMB F
Manufacturer
NXP Semiconductors
Type
Multi-Standard Video Decoderr
Datasheet
1.SAA7118EEB-T.pdf
(177 pages)
Specifications of SAA7118EEB-T
Adc/dac Resolution
9b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-700
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Not Compliant
Other names
SAA7118E/V1,518
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NXP Semiconductors
Table 134. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and B [E0h[7:0]; E1h[7:0]]
Table 135. Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and B [E2h[7:0]; E3h[7:0]]
Table 136. Vertical scaling mode control; register set A [B4h[4 and 0]] and B [E4h[4 and 0]]
[1]
Table 137. Vertical chrominance phase offset ‘00’; register set A [B8h[7:0]] and B [E8h[7:0]]
SAA7118_7
Product data sheet
Vertical luminance scaling
increment
Scale =
zoom
Scale =
Scale = 1, equals 1024
Scale =
Scale =
Vertical chrominance
scaling increment
This value must be set to
the luminance value
YSCY[15:0]
Vertical scaling mode control
Vertical scaling performs linear interpolation between lines
Vertical scaling performs higher order accumulating interpolation, better
alias suppression
No mirroring
Lines are mirrored
Vertical chrominance
phase offset
Offset = 0
Offset =
Offset =
X = don’t care.
1024
1024
1024
1
32
255
63.999
32
32
1
1023
1025
10.7.12 Subaddresses B0h to BFh
= 1 line
(theoretical)
lines
downscale
zoom
downscale 0000
Control bits
A [B1h[7:4]]
B [E1h[7:4]]
YSCY[15:12]
0000
0000
0000
1111
Control bits
A [B3h[7:4]]
B [E3h[7:4]]
YSCC[15:12]
0000
1111
Control bits D7 to D0
YPC07
0
0
1
YPC06
0
0
1
Rev. 07 — 7 July 2008
A [B1h[3:0]]
B [E1h[3:0]]
YSCY[11:8]
0000
0011
0100
0100
1111
A [B3h[3:0]]
B [E3h[3:0]]
YSCC[11:8]
0000
1111
YPC05
0
1
1
Multistandard video decoder with adaptive comb filter
YPC04
0
0
1
A [B0h[7:4]]
B [E0h[7:4]]
YSCY[7:4]
0000
1111
0000
0000
1111
A [B2h[7:4]]
B [E2h[7:4]]
YSCC[7:4]
0000
1111
Control bits D4 and D0
YMIR
X
X
0
1
YPC03
0
0
1
0
YPC02
0
1
[1]
A [B0h[3:0]]
B [E0h[3:0]]
YSCY[3:0]
0001
1111
0000
0001
1111
A [B2h[3:0]]
B [E2h[3:0]]
YSCC[3:0]
0001
1111
YMODE
0
1
X
X
YPC01
0
0
1
SAA7118
© NXP B.V. 2008. All rights reserved.
YPC00
0
0
1
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