PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 81
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PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
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5.0
The PIC18F66K80 family devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”
WDT Resets are covered in
Timer (WDT)”
FIGURE 5-1:
2011 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during Normal Operation
MCLR Reset during Power-Managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM) Reset
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: See
Instruction
INTOSC
RESET
OST/PWRT
Pointer
32 s
Stack
.
( )_IDLE
Brown-out
V
Time-out
(1)
Detect
Sleep
DD
Table 5-2
WDT
Reset
Rise
OST
PWRT
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLRE
10-Bit Ripple Counter
11-Bit Ripple Counter
POR Pulse
for time-out situations.
BOREN
Section 28.2 “Watchdog
1024 Cycles
65.5 ms
Preliminary
.
PIC18F66K80 FAMILY
A simplified block diagram of the On-Chip Reset Circuit
is shown in
5.1
Device Reset events are tracked through the RCON
register
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
of Registers”
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 10.0 “Interrupts”
Section 5.4 “Brown-out Reset (BOR)”
(Register
RCON Register
Figure
.
5-1). The lower five bits of the regis-
5-1.
S
R
Section 5.7 “Reset State
. BOR is covered in
DS39977C-page 81
Q
Enable OST
Enable PWRT
Chip_Reset
.
(2)
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