PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 197
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
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TABLE 11-13: PORTG FUNCTIONS (CONTINUED)
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
2011 Microchip Technology Inc.
RG4/T0CKI
Legend:
Note 1:
PORTG
TRISG
PADCFG1
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by PORTG.
Note 1:
Pin Name
Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared.
Default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set.
Unimplemented on 28-pin devices. Read as ‘ 0 ’.
Function
RDPU
T0CKI
Bit 7
RG4
—
—
(1)
Setting
TRIS
REPU
0
1
x
Bit 6
—
—
I/O
O
I
I
RFPU
I/O Type
Bit 5
—
—
DIG
ST
ST
(1)
Preliminary
LATG<4> data output.
PORTG<4> data input.
Timer0 clock input.
RGPU
TRISG4
Bit 4
RG4
PIC18F66K80 FAMILY
(1)
TRISG3
Bit 3
RG3
—
Description
TRISG2
Bit 2
RG2
—
TRISG1
Bit 1
RG1
—
DS39977C-page 197
CTMUDS
TRISG0
Bit 0
RG0
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