PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 234
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
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PIC18F66K80 FAMILY
16.5
Timer3 can be configured to count freely or the count
can be enabled and disabled using the Timer3 gate
circuitry. This is also referred to as the Timer3 gate
count enable.
The Timer3 gate can also be driven by multiple
selectable sources.
16.5.1
The Timer3 Gate Enable mode is enabled by setting
the TMR3GE bit (TxGCON<7>). The polarity of the
Timer3 Gate Enable mode is configured using the
T3GPOL bit (T3GCON<6>).
When Timer3 Gate Enable mode is enabled, Timer3 will
increment on the rising edge of the Timer3 clock source.
When Timer3 Gate Enable mode is disabled, no incre-
menting will occur and Timer3 will hold the current count.
See
FIGURE 16-2:
DS39977C-page 234
Figure 16-2
Timer3
TMR3GE
T3GPOL
Timer3 Gates
T3GVAL
T3G_IN
T3CKI
TIMER3 GATE COUNT ENABLE
for timing details.
TIMER3 GATE COUNT ENABLE MODE
N
Preliminary
N + 1
TABLE 16-1:
† The clock on which TMR3 is running. For more
T3CLK
information, see T3CLK in
(†)
N + 2
(T3GCON<6>)
T3GPOL
TIMER3 GATE ENABLE
SELECTIONS
0
0
1
1
2011 Microchip Technology Inc.
T3G Pin
N + 3
Figure
0
1
0
1
16-1.
Counts
Holds Count
Holds Count
Counts
N + 4
Operation
Timer3
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