PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 440
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
- Current page: 440 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
DS39977C-page 440
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
In CAN Mode 1 and 2, these bits are forced to ‘ 0 ’.
bit 7
IRXIP: CAN Bus Error Message Received Interrupt Priority bi t
1 = High priority
0 = Low priority
WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
ERRIP: CAN Module Error Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1 = High priority
0 = Low priority
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘ 0 ’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1 = High priority
0 = Low priority
R/W-x
R/W-x
IRXIP
IRXIP
WAKIP
WAKIP
R/W-x
R/W-x
W = Writable bit
‘1’ = Bit is set
ERRIP
ERRIP
R/W-x
R/W-x
Preliminary
TXB2IP
TXBnIP
R/W-x
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
(1)
TXB1IP
TXB1IP
R/W-x
R/W-x
(1)
(1)
TXB0IP
TXB0IP
R/W-x
R/W-x
(1)
(1)
2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IP
RXBnIP
R/W-x
R/W-x
FIFOWMIP
RXB0IP
R/W-x
R/W-x
bit 0
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