SI3206-B-GQ Silicon Laboratories Inc, SI3206-B-GQ Datasheet - Page 112

• Manufacturer Part Number: SI3206-B-GQ
• Description: IC PROSLIC LINE FEED 125V 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3206-B-GQ

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Longitudinal Balanced: 63
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Loop Current Limit: 45mA
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Function: Subscriber Line Interface Concept (SLIC)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 4
• Voltage - Supply: 3.3V
• Current - Supply: *
• Power (watts): *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad
• Includes: *
• Lead Free Status / RoHS Status: Compliant

Si3232
RTPER: Ring Trip Low-pass Filter Coefficient (RAM Address 63)
Reset settings = 0x00
SPEEDUP: DC Settling Speedup Timer (RAM Address 168)
Reset settings = 0x00
SPEEDUPR: Ringing Speedup Timer (RAM Address 169)
Reset settings = 0x00
112
15:0
15:0
15:0
Name
Name
Name
Type
Type
Type
Bit
Bit
Bit
Bit
Bit
Bit
SPEEDUPR[15:0]
SPEEDUP[15:0]
D15
D15
D15
RTPER[15:0]
Name
Name
Name
D14
D14
D14
D13
D13
D13
Ring Trip Low-pass Filter Coefficient.
Programs the low-pass filter coefficient used in the ring trip detection circuit. See
“4.8. Ring Trip Detection” for recommended values.
DC Settling Speedup Timer.
Programs the dc speedup timer that allows quicker settling during loop transitions.
This timer is invoked by the common-mode threshold detectors, CMHITH and
CMLOTH. 1.25 ms/LSB, exception: 0x0000 = 60 ms (default).
Ringing Speedup Timer.
Programs the dc speedup timer that allows quicker settling following ringing bursts.
This timer is invoked by any mode change from the ringing state. 40.96 s range,
1.25 ms/LSB, exception: 0x0000 = 60 ms (default).
D12
D12
D12
D11
D11
D11
D10
D10
D10
Preliminary Rev. 0.96
D9
D9
D9
SPEEDUPR[15:0]
SPEEDUP[15:0]
RTPER[15:0]
D8
D8
D8
R/W
R/W
R/W
D7
D7
D7
Function
Function
Function
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0