EGLXT973QEA3V Cortina Systems Inc, EGLXT973QEA3V Datasheet - Page 81

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Cortina Systems Inc

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
15.0
Figure 29
Table 40
Cortina Systems
Timing Diagrams
The LXT973 Transceiver device meets all timings for MII per the IEEE 802.3u standard.
Figure 29
100BASE-TX Transmit Timing - 4B Mode
MII - 100BASE-TX Transmit Timing Parameters - 4B Mode
®
TXD<3:0>, TXEN, TXER setup to
TXCLK High
TXD<3:0>, TXEN, TXER hold
from TXCLK High
TXEN sampled to CRS asserted
TXEN sampled to CRS de-
asserted
TXEN sampled to twisted-pair
output (Tx latency)
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
production testing.
Parameter
through
Note:
Twisted-Pair
TXD<3:0>
TXCLK
Figure 34 on page 86
Output
TXEN
Twisted-pair output default pins are as follows: DPAP/N_0 and
DPBP/N_1.
CRS
0ns
Sym
t1
t2
t3
t4
t5
t3
t5
t2
t1
refer to MII timings.
Min
12
0
2
2
–
Typ
–
–
4
4
5
1
t4
Max
250ns
–
–
5
5
–
Units
BT
BT
BT
ns
ns
15.0 Timing Diagrams
Conditions
Test
–
–
–
–
–
Page 81