EGLXT973QEA3V Cortina Systems Inc, EGLXT973QEA3V Datasheet - Page 29

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Cortina Systems Inc

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.3.8.2
Figure 7
3.3.8.3
3.4
3.4.1
Cortina Systems
MII Addressing
The MDIO management protocol allows one controller to communicate with multiple
LXT973 Transceiver chips. Pins ADDR_<4:1> determine the base address. Each port
adds its port number to the base address to obtain its port address as shown in
on page
Port Address Scheme
Hardware Control Interface
The LXT973 Transceiver provides a Hardware Control Interface for applications where the
MDIO is not desired. Refer to
additional details.
Operating Requirements
Power Requirements
The LXT973 Transceiver requires five power supply inputs: VCCD, VCCR, VCCT,
VCCPECL, and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD,
VCCR, and VCCT). These inputs may be supplied from a single source although
decoupling is required to each respective ground. The fiber VCCPECL supply can be
connected to either 2.5 V or 3.3 V.
A separate power supply may be used for MII and MDIO (VCCIO) interfaces. The power
supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the same power
source used to supply the controller on the other side of the interface. As a matter of good
practice, these supplies should be as clean as possible.
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
29.
Port 0
Port 1
LXT973
Figure 18, Initialization Sequence, on page 52
Example ADDR<4.1> = 0001
PHY ADDR<4.1> (BASE+0)
ex. 2
PHY ADDR<4.1> (BASE+1)
ex. 3
BASE ADDR<4.1>
Port 0 = 2
Port 1 = 3
3.4 Operating Requirements
for
Figure 7
Page 29