EGLXT973QEA3V Cortina Systems Inc, EGLXT973QEA3V Datasheet - Page 62

• Manufacturer Part Number: EGLXT973QEA3V
• Manufacturer: Cortina Systems Inc

Specifications of EGLXT973QEA3V

• Lead Free Status / RoHS Status: Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
10.6
10.7
10.8
Cortina Systems
Dribble Bits
The LXT973 Transceiver device handles dribbles bits. If one to four dribble bits are
received, the nibble is passed across the interface. The data passed across is padded
with ones, if necessary. If five to seven dribble bits are received, the second nibble is not
sent to the MII bus. This ensures that dribble bits one through seven will not cause a MAC
to discard the frame due to a CRC error. (In 10 Mbps serial mode, all bits are simply
passed across the interface unmodified.)
Transmit Polarity Control
The LXT973 Transceiver allows control over 10BASE-T transmit signal polarity for
simplified integration. In combination with selectable MDI/MDIX mode and automatic
polarity detection, this allows maximum flexibility in pinout definition. (Either of the twisted
pairs may be transmit or receive, and either side of each twisted pair may be set to
positive or negative.)
PHY Address
The LXT973 Transceiver provides four bits to set the PHY address.The least significant bit
is fixed internally with Port 1 always being one address higher than Port 0.
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
10.6 Dribble Bits
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