TJA1080ATS/1,112 NXP Semiconductors, TJA1080ATS/1,112 Datasheet - Page 7

• Manufacturer Part Number: TJA1080ATS/1,112
• Manufacturer: NXP Semiconductors

Specifications of TJA1080ATS/1,112

• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 3.
[1]
[2]
[3]
TJA1080A_4
Product data sheet
Mode
Normal
Receive-only
Go-to-sleep
Standby
Sleep
Pin ERRN provides a serial interface for retrieving diagnostic information.
Valid if V
If wake flag is not set.
Pin signalling in node configuration
IO
and (V
STBN EN
HIGH
HIGH
LOW
LOW
LOW
6.1.3 Bus activity and idle detection
6.2 Operating modes in node configuration
BUF
or V
HIGH error flag
LOW
HIGH error flag
LOW
X
The following mechanisms for activity and idle detection are valid for node and star
configurations in normal power modes:
Additionally, in star configuration, activity and idle can be detected (see
transitions due to activity/idle detection in star configuration):
The TJA1080ATS/2 provides two control pins STBN and EN in order to select one of the
modes of operation in node configuration. See
signalling in node configuration, and
All modes are directly controlled via pins EN and STBN unless an undervoltage situation
is present.
If V
the error flag.
•
•
•
•
•
•
BAT
IO
If the absolute differential voltage on the bus lines is higher than V
t
which results in pin RXD being released:
– If, after bus activity detection, the differential voltage on the bus lines is higher than
– If, after bus activity detection, the differential voltage on the bus lines is lower than
If the absolute differential voltage on the bus lines is lower than V
t
This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)
If pin TXEN is LOW for longer than t
If pin TXEN is HIGH for longer than t
If pin TRXD0 or TRXD1 is LOW for longer than t
pins TRXD0 and TRXD1
If pin TRXD0 and TRXD1 is HIGH for longer than t
pins TRXD0 and TRXD1
det(act)(bus)
det(idle)(bus)
) are present.
and (V
ERRN
LOW
set
set
V
V
IH(dif)
IL(dif)
[2]
[1]
BUF
, pin RXD will go LOW
, pin RXD will go HIGH
, then activity is detected on the bus lines and pin RXEN is switched to LOW
, then idle is detected on the bus lines and pin RXEN is switched to HIGH.
HIGH
error flag
reset
error flag
reset
or V
BAT
Rev. 04 — 19 February 2009
) are within their operating range, pin ERRN indicates the status of
RXEN
LOW
bus
activity
wake flag
set
[2]
HIGH
bus
idle
wake
flag
reset
Figure 3
det(act)(TXEN)
det(idle)(TXEN)
RXD
LOW
bus
DATA_0
wake flag
set
for the timing diagram.
Table 3
[2]
, activity is detected on pin TXEN
det(act)(TRXD)
, idle is detected on pin TXEN
det(idle)(TRXD)
for a detailed description of the pin
HIGH
bus
DATA_1
or idle
wake
flag
reset
TJA1080ATS/2
, activity is detected on
Transmitter INH1 INH2
enabled
disabled
, idle is detected on
FlexRay transceiver
i(dif)det(act)
i(dif)det(act)
© NXP B.V. 2009. All rights reserved.
Figure 6
HIGH HIGH
float
for
for state
for
float
float
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[3]