TJA1080ATS/1,112 NXP Semiconductors, TJA1080ATS/1,112 Datasheet - Page 44

• Manufacturer Part Number: TJA1080ATS/1,112
• Manufacturer: NXP Semiconductors

Specifications of TJA1080ATS/1,112

• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
TJA1080A_4
Product data sheet
14.1.2 Bus error detection
14.1.3 Wake-up signalling via RXD pin
14.1.4 Asymmetric delay and minimum bit time
14.1.5 Transmitter symmetry
14.1.6 Impact of input signals on pin EN
Table 18.
Table 19.
Table 20.
The transmitter symmetry has been improved with respect to the TJA1080. With this
improvement, the TJA1080ATS/2 features less EME than the TJA1080.
Table 21.
TJA1080
The TJA1080 expects that a data frame begins
with a bit value other than the last bit of the
previous data frame.
This is the case for a valid data frame which
begins with the DATA_0 period of the
Transmission Start Sequence (TSS) and ends
with the DATA_1 bit of the Frame End Sequence
(FES). Any violation of this frame format will be
detected by the TJA1080.
Consequently, when transmitting a wake-up
pattern, a bus error will be signalled. This error
indication should be ignored and the status
register should be cleared by reading the vector.
TJA1080
In case of an undervoltage condition at V
RXD might go to LOW level.
For a correct wake-up recognition during a V
undervoltage condition, pin RXEN can be used.
TJA1080
The TJA1080 guarantees minimum bit times of
80 ns for a receiver test signal of 600 mV (see
Figure
(see
TJA1080
Certain pulses on pin EN may lead to a hang-up
of the digital input of pin EN.
Table
13) and asymmetric delay time of 5 ns
14).
Bus error detection differences between TJA1080 and TJA1080ATS/2
Wake-up signalling via RXD differences between TJA1080 and TJA1080ATS/2
Minimum bit time differences between TJA1080 and TJA1080ATS/2
Input signals on pin EN: differences between TJA1080 and TJA1080ATS/2
Rev. 04 — 19 February 2009
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CC
TJA1080ATS/2
The transmission of any valid communication
element, including a wake-up pattern, does not
lead to bus error indication.
TJA1080ATS/2
In case of an undervoltage condition at V
RXD can be used for correct wake-up signalling.
TJA1080ATS/2
The TJA1080ATS/2 guarantees minimum bit
times of 60 ns for a receiver test signal of
400 mV (see
time of less than 5 ns (see
TJA1080ATS/2
This issue has been resolved in the
TJA1080ATS/2
Figure
TJA1080ATS/2
13) and asymmetric delay
FlexRay transceiver
Table
© NXP B.V. 2009. All rights reserved.
14).
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