MCZ33780EG Freescale, MCZ33780EG Datasheet - Page 32

• Manufacturer Part Number: MCZ33780EG
• Manufacturer: Freescale

Specifications of MCZ33780EG

• Operating Supply Voltage (typ): 5/12/15/18/24V
• Operating Supply Voltage (min): 4.75/9V
• Operating Supply Voltage (max): 5.25/25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

SWLEN [3:0]–Short Word Length in Bits
command that will be sent onto the specified DBUS channel.
The reset value for these bits is 1000 (8 bits), which is the
default DSI value. Allowed SWLEN[3:0] values range from
8 bits to 15 bits. If an attempt is made to write a value that is
less than 8 bits, a 1 is automatically written to SWLEN3,
thereby making the register value greater than or equal to 8
bits.
it is necessary to write a full 8 bits into both the DnL and DnH
registers with an SPI command, even though there will be
some MSBs of DnH that are not sent out on the DBUS.
Similarly, to read the data back onto the SPI, it is necessary
to read the full DnL and DnH registers, ignoring unused DnH
bits.
are not allowed. When reading the SWLEN3, bit 0 is always
return; however, the logic interprets the bit as if it were a 1.
SSEN–Spread Spectrum Enable for Channel n
that is specified. With deviation enabled, the DBUS bit
periods will be pseudo-randomly varied from one bit to the
next, while keeping the time between successive Frame
edges constant. The DBUS data rate will be controlled by a
programmable PLL loop, rather than the 4.0 MHz external
clock.
PLLOFF–Spread Spectrum PLL Disable for Channel n
frequency. The PLL adjusts the spread spectrum frequency
up and down by comparing it to a divided down version of the
external 4.0 MHz clock. If the internal spread spectrum clock
is stable, then it is useful to be able to turn off the PLL
updates, thus avoiding clock jitter. In order to change the
frequency of the PLL, PLLOFF must be reset. A write
operation to the frequency offset registers is not allowed
while PLLOFF is set.
32
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI Data Bit
Read/Write
Reset
These bits specify the bit length of the short word
Note If a SWLEN[3:0] value greater than 8 bits is chosen,
The SWLEN3 bit is not used, since words less than 8 bits
This bit enables spread spectrum on the particular channel
This bit disables the PLL loop updating of the DBUS
Bit 7
0
0
Figure 33. Dn Spread Spectrum Control Register Bit Assignments
6
0
0
SSEN
5
0
PLLOFF
4
0
PRBS1
CRCLEN [3:0]–CRC Length in Bits
with commands and read back in. The length is valid for both
short and long word commands. The reset value for these
bits is 0100 (4 bits), which is the default DSI value. Allowed
CRCLEN[3:0] values range from 0 bits (no CRC) to 8 bits. If
an attempt is made to write a value that is greater than 8 bits,
the value 8 (1000) is automatically written into this register.
The CRCLEN[3:0] value overrides the CRCPOLY and
CRCSEED bit values that are beyond what the CRCLEN[3:0]
specifies.
DnSSCTRL REGISTERS
spectrum circuits.
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to this
register. The bit assignments are shown in
PRBS[1:0]–Pseudo-Random Binary Sequence
Register Length for Channel n
Binary Sequence register (PRBS). The PRBS is used to
randomize the DBUS spread spectrum frequencies, and
choosing different lengths will change the XOR tap position
on the PRBS. The following
encoding of this field.
Table 11. PRBS Bit Encoding
3
0
PRBS[1:0]
These bits specify the bit length of CRCs that are sent out
These registers control the operation of the spread
A write to the register will abort any current activity on the
These bits control the length of the Pseudo-Random
00
01
10
11
PRBS0
2
0
PRBS Reg
Length
11
15
6
7
Analog Integrated Circuit Device Data
DEV1
1
0
Table 11
XOR Input A
Freescale Semiconductor
DEV0
10
14
5
6
describes the bit
0
0
Figure
XOR Input B
33.
13
4
5
8