HFIXF1110CC Intel, HFIXF1110CC Datasheet - Page 93

• Manufacturer Part Number: HFIXF1110CC
• Manufacturer: Intel

Specifications of HFIXF1110CC

• Number Of Transceivers: 1
• Screening Level: Commercial
• Mounting: Surface Mount
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

5.7.2
5.7.3
5.7.4
Datasheet
Table 29. Recommended JTAG Termination
Table 30. Supported Boundary Scan Instructions
TAP State Machine
The TAP pins drive a TAP controller, which implements the 16-state machine specified by the
IEEE 1149.1 specification. Following power up, the TAP controller must be reset by one of
following two mechanisms:
This ensures that the boundary scan cells do not block the pin to core connections in theIXF1110
MAC.
Instruction Register and Supported Instructions
The instruction register is a 4-bit register that enacts the boundary scan instructions. After the state
machine resets, the default instruction is IDCODE. The decode logic in the TAP controller selects
the appropriate data register and configures the boundary scan cells for the current instruction. The
table below shows the supported boundary scan instructions.
ID Register
The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI
and TDO. Refer
descriptions.
Signal
TDI
TMS
TCK
1. TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG
•
•
Instruction
interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to
ensure reset of the TAP controller. For more information, refer to
page 93
Asynchronous reset – achieved by pulsing or holding TRST_L low
Synchronous reset – achieved by clocking TCK with five clock pulses while TMS is held or
floats High.
SAMPLE
EXTEST
IDCODE
BYPASS
CLAMP
HIGHZ
Intel
or the IEEE 1149.1 Boundary Scan Specification.
Description
Pull-up through 10 K
Pull-up through 10 K
Pull-up through 10 K
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
toTable 87, “JTAG ID Revision ($ 0x50C)” on page 153
Order Number: 250210, Revision: 009
Code
0000
0001
0101
0110
0111
1111
resistor
resistor
resistor
Intel
®
ID Code Inspection
Sample Boundary
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Clamp Boundary
Float Boundary
External Test
Description
1-bit Bypass
Section 5.7.2, “TAP State Machine” on
Boundary Scan
Boundary Scan
Data Register
for register bit
Bypass
Bypass
Bypass
ID
07-Oct-2005
93