MC33389DDW Freescale, MC33389DDW Datasheet - Page 33

• Manufacturer Part Number: MC33389DDW
• Manufacturer: Freescale

Specifications of MC33389DDW

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (max): 27V
• Operating Supply Voltage (typ): 9/12/15/18/24V
• Operating Supply Voltage (min): 5.5V
• Package Type: SOIC W
• Supply Current: 7mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Register and the SBC SPI Data Register before the
transmission. The new address and R/W bits are already in
the SPI Data Register while the new data and parity bits are
still in an appropriate microcontroller register or memory. This
An appropriate operation in the microcontroller loads the new data and parity into the HC08/12 SPI Data Register (second byte).
In the SBC the internal logic loads P3-P0 and D3-D0 to the location of Bit 15 to Bit 8 in the SBC SPI Data Register, shifting this
data within the remaining eight clock cycles. Please see
transmission. Please see
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 19
After transmission of the first byte, the HC08/12 SPI read buffer contains the old address and R/W bits received from the SBC.
After sixteen clock cycles, the microcontrollers read buffer contains the new parity, and data and is now ready for the next
HC08/12 SPI Data Register
Bit7
Bit7
A5 A4
HC08/12 SPI Data Register
Bit7
A5 A4
0
0
Bit6
Bit6
Bit6
0
0
illustrates content of the HC08/12 SPI Data
old address + R/W in
HC08/12 SPI read buffer
new address + R/W (1st byte)
Bit5
Bit5
A3 A2 A1 A0 RW RW
Bit5
A3 A2 A1 A0
new data + parity (2nd byte)
0
0
Bit4
Bit4
Bit4
0
0
Bit3
Bit3
Bit3
0
0
Figure
Bit2
Bit2
Bit2
0
0
Bit1
Bit1
Bit1
0
0
0
Figure 19. Microcontroller SPI Reading Data - Sequence A
Figure 20. Microcontroller SPI Reading Data - Sequence B
21.
Bit0
Bit0
Bit0
0
0
0
SBC SPI Data Register
Bit15
P3 P2 P1 P0
SBC SPI Data Register
Bit15
A5 A4 A3 A2 A1 A0
Figure
new parity
Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
addressed by the new address
old address + R/W
20.
second byte has to be loaded into the HC08/12 SPI Data
Register after the first byte was transmitted to the SBC.
D3 D2 D1 D0
new data
RW
RW
Bit8
Bit8
Bit7
A5 A4 A3 A2 A1 A0
P3 P2 P1 P0
Bit7
old parity
LOGIC COMMANDS AND REGISTERS
Bit6
Bit6
FUNCTIONAL DEVICE OPERATION
new address + R/W
Bit5
Bit5
Bit4
Bit4
Bit3
D3 D2 D1 D0
Bit3
old data
Bit2
Bit2
Bit1
0
Bit1
Bit0
0
Bit0
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