MC33389DDW Freescale, MC33389DDW Datasheet - Page 31

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MC33389DDW

Manufacturer Part Number
MC33389DDW
Description
Manufacturer
Freescale
Datasheet

Specifications of MC33389DDW

Number Of Transceivers
1
Power Down Mode
Sleep/Standby
Operating Supply Voltage (max)
27V
Operating Supply Voltage (typ)
9/12/15/18/24V
Operating Supply Voltage (min)
5.5V
Package Type
SOIC W
Supply Current
7mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
28
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC33389DDWR2
Manufacturer:
FREESCALE
Quantity:
20 000
entered the MOSI pin starting with Bit15, followed by Bit14,
Bit13, etc., to Bit0. For each fall of the SCLK signal, with CS
held in a logic low state, a data bit is loaded into the shift
register per the tidbit MOSI state.The shift register is full after
sixteen bits of information have been entered.
MISO PIN
the shift register. The MISO pin remains in a high impedance
state until the CS pin goes to a logic low state. The MISO pin
changes state on the rising edge of SCLK and reads out on
the falling edge of SCLK. The MOSI/MISO shifting of data
follows a first-in-first-out protocol with both input and output
words transferring the MSB first.
in table.
Table 16. Module Address Map
Analog Integrated Circuit Device Data
Freescale Semiconductor
Address
The serial output (MISO) pin is the tri-stateable output from
Module Address Map, the module address map is shown
$00A
$00C
$01B
$01D
$01E
$000
$003
$005
$006
$009
$00F
$012
$014
$017
$018
$021
$022
$011
Interrupt mask control register 1
Interrupt mask control register 2
Wake-up input control register
Overtemperature status regist
Wake-up input status register
Cyclic timing control register
Voltage supply status regist
Software watchdog control
Ground shift level register
Interrupt source register 1
Interrupt source register 2
Mode Control Validation
Wake up input real time
Transceiver error status
Transceiver error status
Mode Control Register
Reset source register
V3 control register
register for CANH
register for CANL
RegisterMCVR
information
Register
register
Register Name
WUIRTI
CYTCR
WUICR
TESRH
WUISR
TESRL
SWCR
MCVR
GSLR
OTSR
VSSR
IMR1
IMR2
MCR
ISR1
ISR2
RSR
V3R
Control and Status Reporting of the 33389
33389, while the 33389 reports its status to the MCU. Major
data for control and status reporting are summarized here:
• SPI initialization during start up
• 33389 control during operation
• Watchdog triggering
• Reading status registers of the 33389
Control Data
33389. A control word includes an address of a control
register and the appropriate data (see
the following data will be transferred. Please see
Registers Descriptions on page
• 33389 mode control
• Supply control
• Forced wake-up timing
• Cyclic sense control
• Watchdog control
• Transceiver control
Status Data
MCU. After receiving a valid register address from the MCU,
the 33389 returns the appropriate status. Some of the major
status data are listed below:
• Current operation mode status
• Wake-up sources
• Reset status
• Error status
• Over temperature status
• Transceiver status
Data Transfer
two bytes.The structure of the transferred information is the
same as for control and status reporting. The address field A5
to A0 (Bit 15 to Bit 10) contains the address of a control or
status register in the 33389. RW (Bit 9 and Bit 8) contains the
read/write flag for the data field. The parity field is located at
P3 to P0 (Bit 7 to Bit 4). The data field D3 to D0 (Bit 3 to Bit
0) is part of the two-byte data word. Please see
Table 16. Module Address Map
Address
The MCU is responsible for the control data transfer to the
The control data are transferred from the MCU to the
The status data are transmitted from the 33389 to the
The data to and from the 33389 are transferred in form of
$024
Transceiver control register
Register
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
34.
Figure
Register Name
17). Basically,
Figure
SPI
TCR
17.
33389
31

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