IDT77105L25TF8 IDT, Integrated Device Technology Inc, IDT77105L25TF8 Datasheet - Page 9

• Manufacturer Part Number: IDT77105L25TF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF8

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Transmit Interface
Transmit Interface
Transmit Interface
Transmit Interface
TxData contains the first byte of the cell.
contains valid data.
shake control, TxFull is an active low signal asserted by PHY at least 4
cycles before it is no longer able to accept transmit data. For cell-level
flow control, the assertion of TxClav indicates that the PHY is capable of
receiving an entire 53-byte cell.
transfers on TxData to PHY.
nized to TxClk. All signals are sampled on the rising edge of TxClk. Data
is transferred to the PHY using one of two handshake methods: Octet
(byte)-Level Handshake, Cell-Level Handshake. Handshake method is
selected via setting of the Register 0x00 Bit 1. Octet (byte)-level hand-
shake operates as follows:
IDT77105
Signals
TxData[7:0], TxParity—Transmit Data. TxData[7] is the MSB.
TxSOC—Start Of Cell. Active high signal to be asserted when
TxENB—Enable. Active low signal to be asserted when TxData
TxFull/TxClav—Full/Cell Available. For octet (byte)-level
TxClk—Transmit Clock. Data transfer clock to synchronize data
TxRef—Transmit Reference. 8kHz input for synchronization.
Operation and Timing
Cell transmission is controlled by the external system and is synchro-
!
!
The PHY indicates it can accept data by deasserting TxFull.
(The PHY may assert TxFull at any time which will indicate that
no more than 4 write cycles (bytes) will be accepted.)
If TxEnb is asserted by the external system, data is clocked into
the PHY on the rising edge of TxClk. Note that TxEnb must be
deasserted within 4 cycles of TxFull assertion, and must not be
reasserted until after TxFull deassertion is detected.
TxSOC
TxData
TxClk
TxFul l
TxEnb
X
H1
Figure 3 Transmit Waveform for Octet (byte)-Level Handshake
H2
hand-
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TxClav is only asserted when the PHY can accept transfer of an entire
53-byte cell. TxEnb must remain asserted until at least the last byte of
the cell. If TxClav remains asserted at the end of the cell, TxEnb may
also remain asserted, which allows uninterrupted cell transfer from the
external system to the PHY.
Receive Interface
Receive Interface
Receive Interface
Receive Interface
RxData contains first byte of a cell.
that RxData and RxSOC will be sampled at the start of the next cycle.
control, RxEmpty is an active low signal asserted by the PHY to indi-
cate that in the current cycle there is no valid data available for delivery
over RxData[7:0]. For cell-level flow control, RxClav indicates that an
entire cell is available for immediate transfer over RxData. In both cases,
this signal indicates cycles where there is valid data on RxData/RxSOC.
For Cell-Level Handshake mode, if register 0x02, Bit 6 is set, RxClav
can be deasserted by the PHY for 4 cycles before it is no longer able to
transfer data out.
synchronize transfers on RxData.
data stream.
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The "cell-level" handshake is the same as the byte-level except that
Signals
RxData[7:0], RxParity—Receive Data. RxData[7] is the MSB.
RxSOC—Start Of Cell. Active high signal asserted by PHY when
RxEnb—Enable. Active low signal asserted externally to indicate
RxEmpty/RxClav—Empty/Cell Available. For octet (byte)-level flow
RxClk—Receive Clock. Transfer clock provided externally to
RxRef—Receive Reference. 8kHz output derived from incoming
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