IDT77105L25TF8 IDT, Integrated Device Technology Inc, IDT77105L25TF8 Datasheet - Page 6

• Manufacturer Part Number: IDT77105L25TF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF8

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Functional Description
Functional Description
Functional Description
25MbpsATM Communications Standard
25MbpsATM Communications Standard
25MbpsATM Communications Standard
25MbpsATM Communications Standard
ATM network communications. The physical layer is divided into a Phys-
ical Media Dependent sub layer (PMD) and Transmission Convergence
(TC) sub layer. The PMD sub layer includes the functions for the trans-
mitter, receiver, and timing recovery that allow connection to transmis-
sion media conforming to TIA/EIA 568 (UTP Category 3). The TC sub
layer defines the line coding, scrambling, data framing and synchroniza-
tion, and is described below.
Transmission Convergence (TC) Sub Layer
Transmission Convergence (TC) Sub Layer
Transmission Convergence (TC) Sub Layer
Transmission Convergence (TC) Sub Layer
(SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell, scram-
bles the data, appends a command byte to the beginning of the cell, and
encodes the entire 53 bytes before transmission. These data transfor-
mations ensure that the signal is evenly distributed across the frequency
spectrum. In addition, the serialized bit stream is NRZI coded. An 8kHz
timing sync pulse may be used for isochronous communications.
is distinguished by an escape symbol followed by one of 17 encoded
symbols. Together, this byte forms one of seventeen possible command
bytes. Three command bytes are defined:
IDT77105
The IDT77105 implements the physical layer standard for 25.6Mbps
Introduction
Under control of a switch interface or Segmentation and Reassembly
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte
1. X_X (read: 'escape' symbol followed by another 'escape'): Start-
2.
of-cell with scrambler/descrambler reset.
descrambler reset.
X_4 ('escape' followed by '4'): Start-of-cell without scrambler/
TxData
TxEnb
TxFul l
TxClk
8
Figure 1 Mbps TC Transmit Block Diagram 8. 25 Mbps PHY Xmit Block Diagram
2 Cells
HEC Gen. &
Interface
Insertion
Control,
Octet
4
6 of 24
Clock Input
Scramble
Scrambler
32MHz
Nibble
PRNG
4
of-cell command byte which resets both the transmitter-scrambler and
receiver-descrambler pseudo-random nibble generators (PRNG) to their
initial states. The following cell illustrates the insertion of a start-of-cell
command without scrambler/descrambler reset. During this cell's trans-
mission, an 8kHz timing sync pulse triggers insertion of the X_8 8kHz
timing marker command byte.
page. Cell transmission begins with the Octet Interface Control:
3.
Below is an illustration of the cell structure and command byte usage:
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ...
In the above example, the first ATM cell is preceded by the X_X start-
Transmission Description
Refer to the 25Mbps PHY Transmit Block Diagram on the previous
!
!
!
!
command byte is generated when the 8kHz sync pulse is
detected, and has priority over all line activity (data or command
bytes). It is transmitted immediately when the sync pulse is
detected. When this occurs during a cell transmission, the data
transfer is temporarily interrupted on an octet boundary, and the
X_8 command byte is inserted. This condition is the only allowed
interrupt in an otherwise contiguous transfer.
The SAR (or other upstream system) confirms that the PHY may
accept transmit data by polling the TxFull flag. If this signal is
'high' (PHY xmit buffer not full), the SAR then asserts TxEnb.
The SAR then asserts TxSOC for one cycle of TxCLK, while
putting the first byte on the TxData bus. TxSOC is then
deasserted.
Following bytes are transmitted by putting them onto the TxData
bus while TxEnb is asserted.
4-bit data (MSB first) is asynchronously (to TxClk) sent to the
'Scrambler'.
X_8 ('escape' followed by '8'): 8kHz timing marker. This
Next
4
Encoding
Command
4
Encoding
Insertion
1
NRZI
4b/5b
Byte
Reset
TxRef(8kHz)
TxSOC
Tx +
Tx -
3445 drw 03
September 11, 2000