IDT77105L25TF8 IDT, Integrated Device Technology Inc, IDT77105L25TF8 Datasheet - Page 16

• Manufacturer Part Number: IDT77105L25TF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF8

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Interrupt Status
Interrupt Status
Interrupt Status
Interrupt Status
Address: 0x01
Address: 0x01
Address: 0x01
Address: 0x01
Diagnostic Control
Diagnostic Control
Diagnostic Control
Diagnostic Control
Address: 0x02
Address: 0x02
Address: 0x02
Address: 0x02
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1, 0
Master Type Initial State
Master Type Initial State
IDT77105
—
R
sticky
sticky
sticky
sticky
sticky
sticky
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0 = Bad Signal
0
0
0
0
0
0
0 = normal
0 = UTOPIA
0 = “multi-PHY”
0 = normal
0 = normal
0 = normal
0 = normal
Reserved
Good Signal Bit See definition on pages 10 and 11.
1 = Good Signal
0 = Bad Signal
HEC Error
Interrupt sets when a HEC error is detected in a received cell.
"Short Cell" Received
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected by the TC receiving Start-of-
Cell command bytes with fewer than 53 bytes between them.
Transmit Parity Error
If Bit 4 of Register 0x00 is set (Transmit Data Parity Check), this interrupt flags a transmit data parity error condition. Odd
parity is used.
Receive signal Condition Change This interrupt is set when the received 'signal' changes either from 'bad to good' or from
'good to bad'.
Received Symbol Error Set on receiving a cell with an undefined symbol.
Receive FIFO Overrun Interrupt sets to indicate when the receive FIFO has overflowed.
Force TxClav Deassert
Used during the loopback mode to prevent upstream system from continuing to send data to 77105.
RxClav Operation Select
The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete cell available
for transfer from PHY, RxClav is deasserted following transfer of the last byte out of the PHY to the upstream system. With
this bit set, early deassertion of this signal will occur at the end of Payload byte 44 (as in octet mode for TxFull). This pro-
vides early indication to the upstream system of this impending condition.
"Standard UTOPIA RxClav" = 0
"Cell mode = Byte mode" = 1
Single/Multi-PHY Configuration Select
0 = Single-PHY mode:
1 = Multi-PHY mode:
RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion by clearing this bit.
Insert Transmit Payload Error
Inserts cell payload errors in transmitted cells. This can be used to test error detection and recovery systems at destination
station, or, under loopback control, the local receiving station. This payload error is generated by flipping bit 0 of the last cell
payload byte.
Insert Transmit HEC Error
Insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery systems in down-stream switches, or,
under loopback control, the local receiving station. This HEC error is generated by flipping bit 0 of the HEC byte.
Loopback Control
bit# 1 0
0 0 Normal mode (receive from network)
0 1 Reserved
1 0 PHY Loopback
1 1 Line Loopback
RxData, RxPrty and RxSOC never tri-state
RxEnb = 1 then tri-state RxData, RxPrty, RxSOC
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Function
Function
September 11, 2000