MT48LC32M16A2TG-75 IT:C Micron Technology Inc, MT48LC32M16A2TG-75 IT:C Datasheet - Page 57

• Manufacturer Part Number: MT48LC32M16A2TG-75 IT:C
• Description: DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M16A2TG-75 IT:C

• Density: 512 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Not Compliant

Figure 41:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMH
COMMAND
A0–A9, A12
BA0, BA1
DQM/
CLK
CKE
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
Single READ – With Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. READ command is not allowed else
NOP
t CL
T2
NOP 3
t CH
T3
NOP 3
ENABLE AUTO PRECHARGE
t CMS
57
COLUMN m 2
BANK
T4
READ
t CMH
CAS Latency
t
RAS would be violated.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
512Mb: x4, x8, x16 SDRAM
OUT
NOP
t OH
m
t HZ
©2000 Micron Technology, Inc. All rights reserved.
ACTIVE
BANK
ROW
T7
ROW
Timing Diagrams
T8
NOP
Don’t Care
Undefined