MAX1385BETM+ Maxim Integrated Products, MAX1385BETM+ Datasheet - Page 9

• Manufacturer Part Number: MAX1385BETM+
• Description: RF Wireless Misc IC CTRLR LDMOS BIAS 5V
• Manufacturer: Maxim Integrated Products

Specifications of MAX1385BETM+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI TIMING CHARACTERISTICS (Note 12, See Figure 3)
(GATEV
+2.5V, external V
Note 1: Guaranteed by design.
Note 2: Total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit DACs and the gate driver. They are
Note 3: During power-on reset, the output safe switch is closed. The output safe switch opens once both AV
Note 4: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
Note 5: Offset nulled.
Note 6: Absolute range for analog inputs is from 0 to AV
Note 7: The MAX1385/MAX1386 and external sensor are at the same temperature. External sensor measurement error is tested with
Note 8: The drive current ratio is defined as the large drive current divided by the small drive current in a temperature measure-
Note 9: Guaranteed monotonicity. Accuracy might be degraded at lower V
Note 10: Supply current limits are valid only when digital inputs are at DV
Note 11: Shutdown supply currents are typically 0.1µA. Maximum specification is limited by automated test equipment.
Note 12: All timing specifications referred to V
Note 13: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
Note 14: C
Note 15: For a device operating in an I
Note 16: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 17: A device must provide a data hold time to bridge the undefined part between V
Note 18: Cb = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
SCL Clock Period
SCL High Time
SCL Low Time
DIN Setup Time
DIN Hold Time
SCL Fall to DOUT Transition
CSB Fall to DOUT Enable
CSB Rise to DOUT Disable
CSB Rise or Fall to SCL Rise
CSB Pulse-Width High
Last Clock Rise to CSB Rise
DD
all measured at the GATE1 and GATE2 outputs. Offset removal refers to presetting the drain current after a room tempera-
ture calibration by the user. This effectively removes the channel offset.
voltages are established.
have been removed.
a diode-connected 2N3904.
ment. See the Temperature Measurements section for further details.
when inputs are driven rail-to-rail.
fined region of SCL’s falling edge.
An input circuit with a threshold as low as possible for the falling edge of the SCL signal minimizes this hold time.
linearly interpolated.
PARAMETER
b
= +5.5V for the MAX1385, GATEV
= total capacitance of one bus line in pF; t
REFDAC
_______________________________________________________________________________________
= +2.5V, C
REF
SYMBOL
2
C-compatible system.
t
t
= 0.1µF, T
t
t
CSW
t
t
CSH
t
t
t
t
t
CSS
CH
DH
DO
CP
CL
DS
DV
TR
Dual RF LDMOS Bias Controllers
DD
IH
or V
= +11V for the MAX1386, AV
C
C
C
A
LOAD
LOAD
LOAD
= -40°C to +85°C, unless otherwise noted.)
IL
levels.
R
and t
= 30pF
= 30pF
= 30pF (Note 12)
DD
.
F
are measured between 0.3 x DV
CONDITIONS
with I
DD
REFDAC
or DGND. Timing specifications are only guaranteed
DD
= +5V, DV
.
IH
2
and V
C/SPI Interface
DD
IL
DD
= 2.7V to 5.25V, external V
of the falling edge of the SCL signal.
MIN
62.5
100
25
25
10
25
50
0
and 0.7 x DV
IL
of SCL) to bridge the unde-
TYP
DD
DD
and DV
.
MAX
100
20
40
DD
supply
REFADC
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
=