MAX1385BETM+ Maxim Integrated Products, MAX1385BETM+ Datasheet
MAX1385BETM+
Specifications of MAX1385BETM+
Related parts for MAX1385BETM+
MAX1385BETM+ Summary of contents
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... MAX1385/MAX1386 are available in a 48-pin thin QFN package. RF LDMOS Bias Control in Cellular Base Stations Industrial Process Control PART TEMP RANGE MAX1385AETM+** -40°C to +85°C MAX1385BETM+ -40°C to +85°C MAX1386AETM+** -40°C to +85°C MAX1386BETM+** -40°C to +85° Exposed pad. ** Future product—contact factory for availability. ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ABSOLUTE MAXIMUM RATINGS AV to AGND .........................................................-0. DGND.........................................................-0.3V to +6V DD AGND to DGND.....................................................-0.3V to +0.3V CS1+, CS1-, CS2+, CS2- to GATEGND.................-0.3V to +32V CS1- ...
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ELECTRICAL CHARACTERISTICS (continued) (GATEV = +5.5V for the MAX1385, GATEV DD = +2.5V 0.1µF, unless otherwise noted. T DAC REF PARAMETER SYMBOL Sense-Amplifier Bandwidth LDMOS GATE DRIVER (GAIN = 2 and 4) Output Gate-Drive Voltage Range V Output ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ELECTRICAL CHARACTERISTICS (continued) (GATEV = +5.5V for the MAX1385, GATEV DD = +2.5V 0.1µF, unless otherwise noted. T DAC REF PARAMETER SYMBOL Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching ...
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ELECTRICAL CHARACTERISTICS (continued) (GATEV = +5.5V for the MAX1385, GATEV DD = +2.5V 0.1µF, unless otherwise noted. T DAC REF PARAMETER SYMBOL Capacitive Bypass at REF Power-Supply Rejection Ratio EXTERNAL REFERENCE REFADC Input Voltage Range V REFADC REFADC ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ELECTRICAL CHARACTERISTICS (continued) (GATEV = +5.5V for the MAX1385, GATEV DD = +2.5V 0.1µF, unless otherwise noted. T DAC REF PARAMETER SYMBOL V AND V FOR SDA/DIN AND ...
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I C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 12, see Figure 1) (GATEV = +5.5V for MAX1385, GATEV DD external V = +2.5V 0.1µF, T REFDAC REF PARAMETER SYMBOL Serial-Clock Frequency Bus Free Time Between STOP and START Condition ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2) (GATEV = +5.5V for MAX1385, GATEV DD external V = +2.5V 0.1µF, T REFDAC REF PARAMETER SYMBOL ...
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SPI TIMING CHARACTERISTICS (Note 12, See Figure 3) (GATEV = +5.5V for the MAX1385, GATEV DD +2.5V, external V = +2.5V, C REFDAC REF PARAMETER SYMBOL SCL Clock Period SCL High Time SCL Low Time DIN Setup Time DIN Hold ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface SDA LOW R SCL t HD;STA t HD;DAT S 2 Figure Slow-/Fast-Mode Timing Diagram Sr t RDA t FDA SDA t SU;STA t ...
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MAX1385, GATEV +2.5V 0.1µ +25°C, unless otherwise noted.) REFDAC REF A AV SUPPLY CURRENT DD vs. AV VOLTAGE DD 4 PGA 3.9 CMV = 12V ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface (GATEV = +5.5V for the MAX1385, GATEV +2.5V 0.1µ +25°C, unless otherwise noted.) REFDAC REF A PGAOUT_ 0mV TO 250mV V TRANSIENT RESPONSE ...
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MAX1385, GATEV +2.5V 0.1µ +25°C, unless otherwise noted.) REFDAC REF A INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT COARSE DAC) 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface (GATEV = +5.5V for the MAX1385, GATEV +2.5V 0.1µ +25°C, unless otherwise noted.) REFDAC REF A INTERNAL REFERENCE vs. TEMPERATURE 2.509 2.504 2.499 ...
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PIN NAME 1 DGND Digital Ground Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when 2 SAFE1 programmed channel 1 temperature threshold or current threshold has been reached C-Compatible Address 0/ SPI-Compatible Chip Select. See ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface PIN NAME 23 GATEGND Gate-Drive Amplifier Ground 24 GATEV Gate-Drive Amplifier Supply Input DD 26 OPSAFE2 Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND. Current-Sense ...
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Dual RF LDMOS Bias Controllers DIGITAL CURRENT AND TEMPERATURE DV DD COMPARATORS DGND PGA REGISTERS SCL SDA/DIN REGISTER SERIAL SECTION A0/CSB INTERFACE A1/DOUT A2/N.C. CHANNEL 1 DAC REGISTERS 8-BIT HIGH CODE 8-BIT LOW CODE 10-BIT FINE ADJUST CODE CHANNEL 1 ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface Detailed Description The MAX1385/MAX1386 set and control bias conditions for dual RF LDMOS power devices found in cellular base stations. Each device includes a high-side cur- rent-sense amplifier with programmable ...
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In clock mode 00, power-up, acquisition, conversion, and power-down are all initiated by writing to the Analog- to-Digital Conversion register and performed automati- cally using the internal oscillator. This is the default clock mode. The ADC sets the BUSY output ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ADCIN_ AGND ADCIN_ AGND Figure 4. Equivalent ADC Input Circuit Analog Input Track and Hold The equivalent circuit (Figure 4) shows the MAX1385/MAX1386 ADC input architecture. In track mode, a ...
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Analog-Input Protection Internal ESD protection diodes clamp all analog inputs to AV and AGND, allowing the inputs to swing from DD AGND - 0. 0.3V without damage analog input voltage exceeds the supplies, limit ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface HCAL HIWIPE_ REGISTER THRUHI_ REGISTER THRULO_ REGISTER LOWIPE_ REGISTER LCAL Figure 5. Coarse-DAC Register Diagram FROM 8-BIT COARSE DAC LOAD DAC CONTROL REGISTER (LDAC) FINE_ REGISTER FINECAL_ REGISTER FINECALTHRU_ REGISTER ...
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ADC/DAC References The MAX1385/MAX1386 provide an internal low-noise 2.5V reference for the ADCs, DACs, and temperature sensor. See the Device Configuration Register section for information on configuring the device for external or internal reference. Connect a voltage source to REFADC ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL BUILT- LSBs OF HYSTERESIS BUILT- LSBs OF HYSTERESIS ALARM OUTPUT ASSERTED WHEN MEASURED VALUE ...
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MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD BUILT-IN HYSTERESIS BUILT-IN HYSTERESIS LOW THRESHOLD ALARM OUTPUT OUTPUT- COMPARATOR MODE (ACTIVE LOW) OUTPUT- INTERRUPT MODE (ACTIVE LOW) FLAG REGISTER Figure 8. Window-Threshold-Mode Timing Diagram In single-conversion mode (CKSEL = 11), the BUSY ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL ALARM OUTPUT ASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL *ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE. WHEN IN ...
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Table 2. Register Listing (See Appendix: Recommended Power-Up Code Sequence section) REGISTER DESCRIPTION Analog-to-Digital Conversion Channel 1 High-Current Threshold Channel 1 High-Temperature Threshold Channel 1 Low-Current Threshold Channel 1 Low-Temperature Threshold Channel 2 High-Current Threshold Channel 2 High-Temperature Threshold Channel ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD LOW THRESHOLD ALARM OUTPUT OUTPUT- COMPARATOR MODE (ACTIVE LOW) OUTPUT- INTERRUPT MODE (ACTIVE LOW) FLAG REGISTER READ Figure 10. Hysteresis-Threshold-Mode Timing Diagram Table ...
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Table 4. TL1 and TL2 (Read/Write) D15 D14 D13 D12 (MSB) POR Bit Value (° Don’t care. Table 5. IH1 and IH2 (Read/Write) D15 D14 D13 D12 POR X X ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface Table 7. DCFIG (Read/Write) BIT NAME DATA BIT POR X D15–D10 X Don’t care PG2SET1 D9 0 PGA 2 gain-setting PG2SET0 D8 0 PGA 2 gain-setting PG1SET1 D7 0 PGA ...
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Table 7d. DAC Reference Selection REFDAC1 REFDAC0 DESCRIPTION External. Bypass REFDAC with 0.1µF capacitor to AGND. Internal. Leave REFDAC 1 0 unconnected. Internal. Connect a 0.1µF capacitor REFDAC for extra decoupling and better noise ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface Table 8. ALMSCFG (Read/Write) BIT NAME DATA BIT X D15–D12 ALMSCLR D11 ALARMCMP D10 ALARMHYST1 D9 ALARMHYST0 D8 TALARM2 D7 TWIN2 D6 IALARM2 D5 IWIN2 D4 TALARM1 D3 TWIN1 D2 ...
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Table 10. LOWIPE1 and LOWIPE2 (Read/Write) BIT NAME DATA BIT POR LCAL D15 — D14–D8 X — D7–D0 0000 0000 ALMHCFG (Read/Write) The Hardware Alarm Configuration register controls SAFE1, SAFE2, and ALARM outputs. Write to the Hardware Alarm Configuration register ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface TEXT2 select the temperature at external diode converted. Set ADCSEL1 select voltages at ADCIN1 to be converted. Set IEXT1 to 1 ...
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Table 16. ADCCON (Write) BIT NAME DATA BIT POR X D15–D12 X Don’t care Reserved D11–D8 0 Reserved; set these bits Continuous conversions (repeated scans) CONCONV Noncontinuous conversions (one scan ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface Table 17. SSHUT (Write) BIT NAME DATA BIT POR X D15–D8 X FULLPD D6, D5 FBGON D3 0 OSCPD D2 0 DAC2PD D1 1 DAC1PD ...
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Table 19. SCLR (Write) BIT NAME DATA BIT X D15–D10 FULLRESET D9 ARMRESET CLFIFO D6 HIGHCL2 D5 LOWCL2 D4 FINECL1 D3 HIGHCL1 D2 LOWCL1 D1 FINECL2 D0 Wiper Input register by sending the appropriate read command byte. ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface FIFOOVER is set to 1 when the FIFO overflows. FIFOOVER is set to 0 after reading the Flag register. All threshold-related bits in the Flag register can be cleared at ...
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Table 23. FIFO (Read) DATA BITS D15 D14 D13 D12 ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface WRITE WORD FORMAT ADDRESS R/W ACK 7 BITS 0 WRITE BLOCK FORMAT ADDRESS R/W ACK 7 BITS 0 5-BYTE READ ADDRESS ...
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Table 25. RDFLAG (Read) BIT NAME DATA BIT X D15– D12 ADCBUSY D11 ALUBUSY D10 FIFOEMP D9 FIFOOVER D8 HIGHI2 D7 LOWI2 D6 HIGHT2 D5 LOWT2 D4 HIGHI1 D3 LOWI1 D2 HIGHT1 D1 LOWT1 D0 The MAX1385/MAX1386 use read and ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface ADDRESS BITS Sr ADDRESS 7 BITS Figure 12. Write/Readback Sequence ADDRESS R ACK 7 BITS 0 Sr ADDRESS 7 BITS Figure 13. Read-Modify-Write ...
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C7 C6 SDA 1 2 SCL Figure 15. Command Byte D15 D12 D14 D13 D11 SDA SCL Figure 16. Data Bytes SDA SCL Figure 17. START and STOP Conditions high-speed mode (HS mode), allowing bus ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface CSB SCL DIN CR/W Figure 18. SPI Write Format CSB SCL DIN CR/W DOUT Figure 19. SPI ...
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SDA SCL Figure 21. Changing to HS Mode MASTER TO SLAVE SLAVE TO MASTER FS MODE S MASTER CODE A Figure 22. Changing to FS Mode or Staying in HS Mode Applications Information ADC Clock Mode 11 ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface t CNV11 CNVST BUSY INTERNAL INT REFERENCE POWERS UP IN ~60µs USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER TO SET UP CONVERSION SCAN OF INTERNAL TEMPERATURE, PGAOUT1, AND ADCIN1 Figure ...
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Table 27. Basic Software Initialization COMMAND DATA BYTE WORD 0x64 0x0008 Bring the device out of shutdown mode. 0x64 0x0008 Set internal reference and both DAC channels on. 0x20 0x02A8 Set the channel 1 high-temperature threshold to +85°C. 0x22 0x0EC0 ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface Table 28. DAC Write Commands Without Autocalibration ACTION REQUIRED Update fine DAC_ without triggering autocalibration. Update high wiper coarse DAC_ without triggering autocalibration. Update low wiper coarse DAC_ without triggering ...
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Table 29. DAC Write Commands with Autocalibration ACTION REQUIRED Update fine DAC_ and trigger autocalibration. Update high wiper coarse DAC_ and trigger autocalibration. Update low wiper coarse DAC_ and trigger autocalibration. Immediately update fine DAC_ and trigger autocalibration. Immediately update ...
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Dual RF LDMOS Bias Controllers 2 with I C/SPI Interface 5V SCL SDA MICROCONTROLLER (AT LDMOSFET) (AT LDMOSFET) 5V *SELECT R AND C BASED ON DESIRED FILTER CUT-OFF FREQUENCY LIMIT R TO MINIMIZE OFFSET ERRORS ______________________________________________________________________________________ ...
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Pin Configuration TOP VIEW N.C. 37 N. PGAOUT1 A2/N.C. 41 N.C. 42 MAX1385 SCL 43 MAX1386 SDA/DIN 44 A1/DOUT 45 46 N.C. BUSY 47 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 52 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products of the part, irrespective of power-supply ramp speed and starts the device regulating to 312 ...