MT48LC16M16A2FG-75:D Micron Technology Inc, MT48LC16M16A2FG-75:D Datasheet - Page 39

• Manufacturer Part Number: MT48LC16M16A2FG-75:D
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2FG-75:D

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54VFBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Table 18: Truth Table – Current State Bank n, Command to Bank m
Notes 1–6 apply to all parameters and conditions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Current State
Any
Idle
Row activating, active, or
precharging
Read
(auto precharge disabled)
Write
(auto precharge disabled)
Read
(with auto precharge)
Write
(with auto precharge)
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; for example, the cur-
3. Current state definitions:
after
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are cov-
ered below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
RAS# CAS# WE# Command/Action
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise supported for bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
39
n-1
was HIGH and CKE
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP has been met.
256Mb: x4, x8, x16 SDRAM
n
is HIGH (Table 19 (page 41)), and
t
RCD has been met. No data bursts/
© 1999 Micron Technology, Inc. All rights reserved.
Truth Tables
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9