8523BGLF Integrated Device Technology (Idt), 8523BGLF Datasheet - Page 17

• Manufacturer Part Number: 8523BGLF
• Description: Clock Driver 2-IN HSTL 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8523BGLF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: CML|HCSL|HSTL|LVDS|LVPECL|SSTL
• Maximum Output Frequency: 650 MHz
• Operating Supply Voltage: 3.3 V

ICS8523 Data Sheet
Revision History Sheet
ICS8523CG REVISION E JANUARY 24, 2011
Rev
B
B
B
C
C
C
C
C
C
D
E
Table
T4D
T4D
T4C
T4D
T5
T5
T2
T9
T8
T5
T5
11 - 12
Page
8-10
15
16
10
11
5
5
3
3
5
1
2
4
5
1
9
6
1
4
4
5
5
6
8
8
9
Description of Change
HSTL table - added V
AC Characteristics table - t
changed Max. from 2.0ns to 1.6ns.
Updated Figure 1, CLK_EN Timing Diagram.
Updated Figure 1, CLK_EN Timing Diagram.
AC Characteristics table - t
tsk(pp) row, changed Max. from 150ps to 200ps.
Revised Features section, Bullet 1,6 - took out 1.8V
In the Application Information section, added Schematic Examples.
Pin Characteristics Table - changed C
Absolute Maximum Ratings - changed Output rating.
HSTL DC Characteristics Table - changed V
Power Considerations - changed Total Power Dissipation to reflect V
Calculations changed due to new Total Power Dissipation.
Changed LVHSTL to HSTL throughout data sheet.
Features section - added Lead-Free bullet.
Updated LVPECL Clock Input Interface section.
Added Lead-Free marking to Ordering Information table.
Ordering Information Table - in the Part/Order Number and Marking columns, changed die
revision from “B” to “C”.
AC Characteristics Table - changed t
Features Section - added Additive Phase Jitter bullets.
the datasheet.
Absolute Maximum Ratings - corrected Outputs Rating.
Differential DC Characteristics Table - updated notes.
LVPECL DC Characteristics Table - updated notes.
AC Characteristics Table - added Buffer Additive Phase Jitter specs.
Added Additive Phase Jitter plot.
Corrected Output Duty Cycle/Pulse Width/Period diagram.
Updated Wiring the Differential Input to Accept Single-ended Levels application note.
Updated 3.3V Differential Clock Input Interface application note.
Updated 3.3V LVPECL Clock Input Interface application note.
Added HSTL Output Termination diagram.
Pin Assignment has nCLK, nPCLK. Changed CLK, PCLK to nCLK, nPCLK throughout
Add thermal note and updated NOTE 4.
SWING
PD
PD
row to HSTL DC Characteristics Table.
row, added value of 1.3ns to Min.;
row, changed Min. from 1.3ns to 1.0ns.
17
R
IN
/t
F
4pF max. to 4pF typical.
minimum from 300ps to 250ps.
OH
1V min. to 0.9V min.
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
OH
©2011 Integrated Device Technology, Inc.
change.
10/17/01
10/25/02
7/31/01
11/2/01
1/11/02
6/20/03
9/13/04
3/13/07
1/24/11
5/6/02
3/2/07
Date