78Q8430-128CGT/F Maxim Integrated Products, 78Q8430-128CGT/F Datasheet - Page 71

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78Q8430-128CGT/F

Manufacturer Part Number
78Q8430-128CGT/F
Description
Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
Manufacturer
Maxim Integrated Products
Datasheet
DS_8430_001
7.6.35 Overflow/Underrun Interrupt Register
Note: All bits are cleared on read.
7.6.36 Overflow/Underrun Mask Register
7.6.37 Transmit RMON Interrupt Register
Note: All bits are cleared on read.
Rev. 1.2
Name: OUIR
Bits
31
30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Name: OUMR
Bits
31:0
Name: TRIR
Bits
31:0
Type
Type
Type
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Default
0x0000
0x0000
0000
0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
00
00
00
00
00
00
00
00
0
0
Description
QUE Data Overflow
Overflow condition detected on QUE 7.
QUE Data Underrun
Under-run condition detected on QUE 7.
Reserved
QUE 6
QUE Data Overflow and QUE Data Underrun bits for QUE 6.
Reserved
QUE 5
QUE Data Overflow and QUE Data Underrun bits for QUE 5.
Reserved
QUE 4
QUE Data Overflow and QUE Data Underrun bits for QUE 4.
Reserved
QUE 3
QUE Data Overflow and QUE Data Underrun bits for QUE 3.
Reserved
QUE 2
QUE Data Overflow and QUE Data Underrun bits for QUE 2.
Reserved
QUE 1
QUE Data Overflow and QUE Data Underrun bits for QUE 1.
Reserved
QUE 0
QUE Data Overflow and QUE Data Underrun bits for QUE 0.
Reserved
Description
Overflow/Underrun Interrupt Mask
When a bit is set, it enables the overflow/underrun interrupt for the
corresponding bit in the OUIR. When a bit is clear, the corresponding
bit in the OUIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
Description
RMON Tx Counter Rollover
Set when the RMON Tx counter with the same index number as the bit
number has rolled over.
Block: CTL
Block: CTL
Block: CTL
Address: 0x1C8
Address: 0x1CC
Address: 0x1D0
78Q8430 Data Sheet
71

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