78Q8430-128CGT/F Maxim Integrated Products, 78Q8430-128CGT/F Datasheet - Page 67

• Manufacturer Part Number: 78Q8430-128CGT/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
7.6.25 Host Not Responding Count Register
7.6.26 Wake Up Status Register
7.6.27 Water Mark Values Register
Note: For all watermarks, a value of zero will disable the related feature.
7.6.28 Power Management Capabilities
Rev. 1.2
Name: HNRCR
Bits
31:0
Name: WUSR
Bits
31:8
7:0
Name: WMVR
Bits
31
30:24
23
22:16
15
14:8
7
6:0
Name: PMCAP
Bits
31:27
26
25
24:20
19
18:16
Type
Type
Type
Type
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
X
X
X
X
X
Default
Default
Default
Default
0x7D
0x00
0x04
0x00
0x02
0x00
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
Reset Val: 0x0000_0400
Reset Val: 0x120A_4801
010
0
1
1
Description
Count
Number of system cycles to wait for the host to respond to a wake
condition before sending an HNR response.
Description
Reserved
Class
The classification result that triggered the wake up event.
Description
Reserved
Free
A count of the number of free memory blocks in the memory manager.
Reserved
Interrupt
Minimum number of free blocks before the host is interrupted.
Reserved
Headroom
Minimum number of free blocks before the MAC receiver is halted.
Reserved
PAUSE
Minimum number of free blocks before the PAUSE packet is sent.
Description
Support
Power management events supported. This field always reads back
00010b to indicate PME from D1 is supported.
D2 Support
Reads back 0 to indicate D2 is not supported.
D1 Support
Reads back 1 to indicate D1 is supported.
Init
Reads back 00000b to indicate no device specific initialization.
CLK
Reads back 1 to indicate the clock (BUSCLK) is needed for PME
operation.
VER
Reads back 010b to indicate specification version 1.1 compliance.
Block: CTL
Block: CTL
Block: CTL
Block: CTL
Address: 0x188
Address: 0x18C
Address: 0x190
Address: 0x198
78Q8430 Data Sheet
67