78Q8430-128CGT/F Maxim Integrated Products, 78Q8430-128CGT/F Datasheet - Page 16

• Manufacturer Part Number: 78Q8430-128CGT/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

78Q8430 Data Sheet
3.2.8
Notes:
3.2.9
16
Signal
BUSMODE
CLKMODE
WAITMODE
ENDIAN0
ENDIAN1
BOOTSZ1
BOOTSZ0
Signal
TRST
TCLK
TMS
TDI
TDO
1. The internal PHY should never be powered down when the internal system clock is selected by
2. There is no external visibility for the system clock when the internal clock mode is selected. The
Mode Pins
the CLKMODE pin (CLKMODE=1)
GBI interface must therefore always be used in asynchronous bus mode.
JTAG Pins
Pin Number
Pin Number
100
83
85
84
79
80
81
1
5
6
3
4
Table 9: Chip Mode Pin Descriptions
Type
Type
Table 10: JTAG Pin Descriptions
IU
IU
O
I
I
I
I
I
I
I
I
I
Description
BUSMODE, CLKMODE, WAITMODE Configuration
0,0,0 = Sync bus, ext. system clock, memwait act low
0,0,1 = Sync bus, ext. system clock, memwait act high
0,1,0 = Reserved
0,1,1 = Reserved
1,0,0 = Async bus, ext. system clock, memwait act low
1,0,1 = Async bus, ext. system clock, memwait act high
1,1,0 = Async bus, int. system clock, memwait act low
1,1,1 = Async bus, int. system clock, memwait act high
Data Bus Endian Select
0,0 = Big endian (MSB at high bit positions)
0,1 = Bytes are little endian inside 16-bit words
1,0 = Word endian (MSW at low bit positions)
1,1 = Little endian (MSB at low bit positions)
GBI Bus Size
BOOTSZ[1:0]: is strapped to indicate the GBI bus size:
00 = Bus is 32 bits wide
01 = Bus is 16 bits wide. Only DATA[15:0] are used.
10 = Bus is 8 bits wide. Only DATA[7:0] are used.
11 = Reserved
Description
Test Reset (active low)
System provided reset for JTAG logic.
Test Clock
System provided clock for JTAG logic.
Test Mode Select
Enables JTAG boundary scan using serial in/serial out ports.
Sampled on rising edge of TCLK.
Test Data In
Serial input port for clocking in test data to be shifted to the
output at the end of the boundary scan chain (TDO).
Test Data Out
Serial output port for clocking out test data shifted from the
input at the beginning of the boundary scan chain (TDI).
DS_8430_001
Rev. 1.2