KSZ8001L TR Micrel Inc, KSZ8001L TR Datasheet - Page 17

• Manufacturer Part Number: KSZ8001L TR
• Description: 10/100 BASE-TX/FX Physical Layer Transceiver With LinkMD Cable Diagnostics, Single 3.3V Supply, 48-LQFP,
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8001L TR

• Protocol: MII, RMII, SMII
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1620 - BOARD EVALUATION FOR KSZ8001L
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: KSZ8001LTR; KSZ8001LTR

March 2006
Micrel
SMII Signal Definition
SMII is composed of two signals per port, a global synchronization signal, and a global 125MHz reference clock. All signals are
synchronous to the clock. All SMII I/F uses a common 125MHz reference clock and SYNC signals that are synchronous to the
reference clock. There are two signals in SMII from MAC-to-PHY for each port (TXD and TxSYNC), and one signal per port from
PHY-to-MAC (RXD).
The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements:
SMII Signals
Receive Path
Receive data and control information are signaled in ten bit segments. In 100Mbit mode, each segment represents a new byte of
data. In 10Mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC
can simply any one of every 10 segment ion 10Mbit mode.
Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
Receive Sequence Diagram
RX – Bit Description
RXD7-0 are used to convey packet data, RX_ER, and PHY status. The MAC can infer the meaning of RXD on a segment-by-basis
by encoding the two control bits.
R X _ S Y N C
RX contains all of the information found on the receive path of the standard MII.
R X _ C L K
Signal Name
RX
TX
SYNC
Clock
Bits
CRS
RX_DV
RXD7-0
•
•
•
•
•
R X
Convey complete MII information between a 10/100 PHY and MAC with two pins per port.
Allow a multi-port MAC/PHY communication with one system clock.
Operate in both half and full duplex.
Per packet switching between 10Mbit and 100Mbit data rates.
Allow direct MAC-to-MAC communication.
C R S
R X _ D V
Purpose
Carrier Sense – identical to MII, except that it is not an asynchronous signal
Receive Data Valid – identical to MII
Encoded Data, see the RXD0-7 Encoding table
From
PHY
MAC
MAC
System
R X D 0
R X D 1
R X D 2
17
To
MAC
PHY
PHY
MAC&PHY
R X D 3
R X D 4
Use
Receive Data and Control
Transmit Data and Control
Synchronization
Synchronization
R X D 5
R X D 6
Revision 1.03
R X D 7
KSZ8001