CYD18S72V-100BBC Cypress Semiconductor Corp, CYD18S72V-100BBC Datasheet - Page 22

• Manufacturer Part Number: CYD18S72V-100BBC
• Description: IC,SYNC SRAM,256KX72,CMOS,BGA,484PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S72V-100BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 18M (256K x 72)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Waveforms
Mailbox Interrupt Timing
Notes
Document Number : 38-06069 Rev. *K
Counter Interrupt and Retransmit
48. CE
49. CNTINT is always driven.
50. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
51. The mask register assumed to have the value of 1FFFFh.
52. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
53. CE
54. Address “1FFFF” is the mailbox location for R_Port.
55. L_Port is configured for Write operation, and R_Port is configured for Read operation.
56. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
57. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
CNT/MSK
CLK
L_PORT
ADDRESS
INT
CLK
R_PORT
ADDRESS
ADS
COUNTER
INTERNAL
ADDRESS
CNTEN
CLK
CNTINT
R
L
R
0
0
= OE = BE0 – BE7 = LOW; CE
= OE = ADS = CNTEN = LOW; CE
t
SCM
1FFFC
t
CH2
t
CH2
t
CH2
t
HCM
t
CYC2
t
CYC2
t
[53, 54, 55, 56, 57]
CYC2
t
CL2
1
t
= R/W = CNTRST = MRST = HIGH.
(continued)
CL2
t
t
SA
3FFFF
CL2
1
= CNTRST = MRST = CNT/MSK = HIGH.
1FFFD
t
SA
A
t
HA
m
[48, 49, 50, 51, 52]
t
t
HA
SINT
A
n
1FFFE
A
m+1
t
SCINT
A
n+1
1FFFF
3FFFF
t
RCINT
t
RINT
Last_Loaded
A
n+2
A
m+3
Last_Loaded +1
A
n+3
A
m+4
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