CY7C1347G-200AXC Cypress Semiconductor Corp, CY7C1347G-200AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1347G-200AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347G-200AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 4.5Mb
• Access Time (max): 2.8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 265mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2115; CY7C1347G-200AXC

Pin Definitions
Document #: 38-05516 Rev. *H
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
DQ
DQP
DQP
V
V
V
V
MODE
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
0
DD
SS
DDQ
SSQ
,A
1
2
3
A,
C,
A,
C,
Name
1
A,
C,
BW
BW
,A
DQ
DQ
DQP
DQP
B,
B
D
D
B,
D
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
Power Supply
Ground
I/O Power Supply
I/O Ground
Input-
Static
–
I/O
Address Inputs Used to Select One of the 128 K Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
the 2-bit counter.
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
a new external address is loaded.
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE
Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs
are placed in a tristate condition.
Power Supply Inputs to the Core of the Device
Ground for the Core of the Device
Power Supply for the I/O circuitry
Ground for the I/O circuitry
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode pin has an internal pull-up.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the
die.
2
3
3
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
to select or deselect the device. CE
1
is deasserted HIGH.
Description
3
2
is sampled only when a new external address is loaded.
is sampled only when a new external address is loaded.
1
, CE
2
, and CE
1
is HIGH. CE
3
are sampled active. A
[1:0]
[1:0]
[A:D]
1
are also loaded into the
are also loaded into the
and BWE).
is sampled only when
CY7C1347G
DDQ
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[1:0]
or left
feeds
2
1
1
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