CY7C1347G-200AXC Cypress Semiconductor Corp, CY7C1347G-200AXC Datasheet
CY7C1347G-200AXC
Specifications of CY7C1347G-200AXC
CY7C1347G-200AXC
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CY7C1347G-200AXC Summary of contents
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... K × 36) Pipelined Sync SRAM Functional Description The CY7C1347G SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2 the 3.3 V level. The I/O pins are 3.3 V tolerant when V = 2.5 V. All synchronous inputs pass through input DDQ registers controlled by the rising edge of the clock ...
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... BURST COUNTER AND CLR Q0 LOGIC DQ ,DQP D D BYTE WRITE DRIVER BYTE WRITE DRIVER MEMORY ARRAY DQ DQP BYTE WRITE DRIVER DQ DQP BYTE WRITE DRIVER PIPELINED ENABLE CY7C1347G OUTPUT OUTPUT SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D INPUT REGISTERS Page [+] Feedback ...
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... Thermal Resistance ........................................................ 12 Switching Characteristics .............................................. 13 Switching Waveforms .................................................... 14 Ordering Information ...................................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 22 Reference Documents .................................................... 22 Document Conventions ................................................. 22 Units of Measure ....................................................... 22 Port Nomenclature .................................................... 22 Bit Field Nomenclature .............................................. 22 Glossary .......................................................................... 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC Solutions ......................................................... 24 CY7C1347G Page [+] Feedback ...
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... DDQ V 5 SSQ BYTE SSQ V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ DQP 30 D Document #: 38-05516 Rev. *H Figure 1. 100-Pin TQFP Pinout CY7C1347G CY7C1347G DQP DDQ V 76 SSQ BYTE SSQ V 70 DDQ DDQ 60 V SSQ BYTE SSQ V 54 DDQ 53 DQ ...
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... V CLK BWE DQP MODE NC/72M Figure 3. 165-Ball FBGA Pinout BWE CLK NC/18M CY7C1347G DDQ CE NC/576 NC/1G DQP DDQ DDQ DDQ DQP NC/36M DDQ ADSC ADV ADSP A NC/576 NC/1G DQP SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP SS DDQ A A NC/9 M ...
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... ADSP is ignored select or deselect the device sampled only when a new external address is loaded select or deselect the device sampled only when a new external address is loaded deasserted HIGH. 1 CY7C1347G , CE , and CE are sampled active. A feeds [1:0] and BWE). [A:D] is HIGH. CE ...
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... A synchronous self timed write mechanism has been provided to simplify the write opera- tions. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output drivers ...
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... Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed that implements either an interleaved or linear burst [1:0] sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input ...
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... Read cycle, suspend burst Current Write cycle, suspend burst Current Write cycle, suspend burst Current Table 2. Partial Truth Table for Read/Write The partial truth table for read/write for part number CY7C1347G follow. Function Read Read Write byte A – Write byte B – DQ ...
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... OH = – < DDQ ≤ V output disabled I DDQ, is valid. Appropriate write is based on which byte write is active. x CY7C1347G Test Typ Max* Unit Conditions Logical 25 °C 361 394 single-bit upsets Logical 25 °C 0 0.01 multi-bit upsets Single event 85 °C 0 0.1 latch-up Accelerated Neutron SER Testing and Calculation of ...
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... MHz 7.5 ns cycle, 133 MHz , device deselected, DD ≥ V ≤ /2). Undershoot: V (AC) > –2 V (pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1347G Min Max 325 265 240 225 120 110 100 90 40 105 /2). CYC < ...
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... R = 317 Ω 3 OUTPUT GND 351 Ω Including JIG and (b) scope R = 1667 Ω 2 DDQ OUTPUT GND 1538 Ω Including JIG and scope (b) CY7C1347G 119 BGA 165 FBGA Max Max 119 BGA 165 FBGA Package Package 34.1 20.3 14.0 4.6 All input pulses ...
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... V AC Test Loads and Waveforms on page and t is less than t to eliminate bus contention between SRAMs when sharing the same data bus. OELZ CHZ CLZ = 2 all datasheets. DDQ unless otherwise noted. CY7C1347G –166 –133 Max Min Max Min Max 1 1 6.0 7 ...
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... OEV OEHZ t OELZ t DOH Q(A2 Q(A1) BURST READ DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1347G A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Document #: 38-05516 Rev. *H [16, 17] Figure 6. Write Cycle Timing ADSC extends burst A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. x CY7C1347G t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 19 HIGH. Document #: 38-05516 Rev. *H [16, 18, 19] Figure 7. Read/Write Cycle Timing WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED CY7C1347G A5 A6 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See 21. DQs are in High Z when exiting ZZ sleep mode. Document #: 38-05516 Rev. *H [20, 21] Figure 8. ZZ Mode Timing DESELECT or READ Only High-Z DON’T CARE Table 1 on page 8 for all possible signal conditions to deselect the device. CY7C1347G t ZZREC t RZZI Page [+] Feedback ...
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... Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-Free CY7C1347G-166AXI 51-85050 100-Pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-Free 200 CY7C1347G-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-Free 250 CY7C1347G-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-Free Document #: 38-05516 Rev ...
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... Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) Document #: 38-05516 Rev. *H CY7C1347G 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 38-05516 Rev. *H Figure 10. 119-Ball BGA (14 × 22 × 2.4 mm) CY7C1347G 51-85115 *C Page [+] Feedback ...
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... ODT on-die termination PLL phase-locked loop QDR quad data rate TAP test access port TCK test clock TDO test data out TDI test data in TMS test mode select Document #: 38-05516 Rev. *H Figure 11. 165-Ball FBGA (13 × 15 × 1.4 mm) CY7C1347G 51-85180 *C Page [+] Feedback ...
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... Document History Page Document Title: CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM Document Number: 38-05516 Orig. of Submission Revision ECN Change Date ** 224364 RKF See ECN *A 276690 VBL See ECN *B 333625 SYT See ECN *C 419256 RXU See ECN *D 480124 VKN See ECN ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05516 Rev. *H All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised August 2, 2010 CY7C1347G PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...