CY7C0853V-100BBC Cypress Semiconductor Corp, CY7C0853V-100BBC Datasheet - Page 7

• Manufacturer Part Number: CY7C0853V-100BBC
• Description: IC,SYNC SRAM,256KX36,CMOS,BGA,172PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-06070 Rev. *D
Master Reset
The FLEx36 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx36 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0853V.
The highest memory location, 3FFFF is the mailbox for the
right port and 3FFFE is the mailbox for the left port. Table 2
Table 2. Interrupt Operation Example
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
Notes:
CLK
4.
5.
6.
7.
8.
9.
X
CE is internal signal. CE = LOW if CE
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
OE is “Don’t Care” for mailbox operation.
At least one of B0, B1, B2, or B3 must be LOW.
A16x is a NC for CY7C0851V, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850V, therefore the Interrupt Addresses
are 7FFF and 6FFF.
“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Counter operation and mask register operation is independent of chip enables.
MRST
Function
H
H
H
H
H
H
H
H
H
L
L
Flag
R
L
Flag
Flag
R
CNT/MSK
Flag
X
H
H
H
H
H
L
L
L
L
R/W
CNTRST
H
X
X
L
0
L
X
H
H
H
H
H
H
H
L
L
= LOW and CE
CE
[1, 4, 5, 6, 7]
X
X
L
L
L
ADS
X
X
H
H
X
H
L
L
L
L
1
Left Port
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CNTEN
A
3FFFE
3FFFF
0L–17L
H
H
H
X
X
L
L
X
L
X
X
X
Master Reset
Counter Reset
Counter Load
Counter Readback Read out counter internal value on
Counter Increment Internally increment address counter
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
shows that in order to set the INT
the left port to address 3FFFF will assert INT
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 3FFFF location by the right port will reset
INT
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Operation
R
INT
HIGH. At least one byte has to be active in order for a
X
X
H
L
L
R/W
X
H
X
L
R
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
address lines.
value.
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
Load mask register with value presented
on the address lines.
Read out mask register value on address
lines.
Operation undefined
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
CE
X
X
L
L
[8, 9]
R
Right Port
Description
R
flag, a Write operation by
A
3FFFE
3FFFF
0R–17R
X
X
R
LOW. At least
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INT
H
X
X
L
R