CY7C0853V-133BBXI Cypress Semiconductor Corp, CY7C0853V-133BBXI Datasheet
CY7C0853V-133BBXI
Specifications of CY7C0853V-133BBXI
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CY7C0853V-133BBXI Summary of contents
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... JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0853V/CY7C0853AV device in this family has limited features. Please see Operations” on page 9. 1-Mbit 2-Mbit ...
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... Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV I/O I/O Control Control True Dual-Ported RAM Array Address Address Decode Decode TMS Reset MRST TDO TDI JTAG Logic TCK CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV –DQ 27R 35R 9 DQ – ...
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... Mask Reset Operation ............................................... 10 Mask Load Operation ................................................ 10 Mask Readback Operation ........................................ 10 Counting by Two ....................................................... 10 IEEE 1149.1 Serial Boundary Scan (JTAG) ................... 13 Performing a TAP Reset ........................................... 13 Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Maximum Ratings ........................................................... 14 Operating Range ............................................................. 14 Electrical Characteristics ............................................... 14 Capacitance .................................................................... 14 Switching Characteristics 1.............................................. 5 JTAG Timing ................................................................... 17 Ordering Information ...................................................... 29 Ordering Code Definition ........................................... 30 Package Diagrams ...
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... VDD VSS DQ25L DQ19L VSS VSS DQ19R TDI DQ7L DQ2L DQ2R DQ7R DQ5L DQ3L DQ0L DQ0R DQ3R DQ4L VDD DQ1L DQ1R VDD CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV DQ13R VSS CNTINTR DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R A0R INTR DQ27R DQ31R A1R NC DQ28R DQ34R DQ35R ...
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... DQ19L VSS VSS DQ19R DQ18L TDI DQ7L DQ2L DQ2R DQ7R DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R VSS DQ4L VDD DQ1L DQ1R VDD CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV DQ13R VSS NC DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R A0R INTR DQ27R DQ31R A1R A17R DQ28R DQ34R DQ35R ...
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... A 11L 36 A 12L 13L 40 A 14L [ 15L [ 16L 43 DQ 24L 44 DQ 20L Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV CY7C0850AV CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 SS V 124 DD A 123 4R A 122 ...
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... V Ground inputs Power inputs. DD Notes 3. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits 4. These pins are not available for CY7C0853V/CY7C0853AV device. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Description . MAX is asserted LOW when the right ...
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... H H Counter hold X X Mask reset L L Mask load L H Mask readback H X Reserved = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and 1 CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV flag, a Write R Right Port R 0R–17R 3FFFF L L 3FFFE ...
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... This section describes the features only apply to CY7C0850AV/CY7C0851V/0851AV/CY7C0852V/0852AV devices, but not to the CY7C0853V/0853AV device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array ...
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... Master reset (MRST) also resets the mask register to all “1s.” Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2 From the most significant bit to the least significant bit, permitted values have zero or more “ ...
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... Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [14] Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter Page [+] Feedback ...
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... The “X” in this diagram represents the counter upper bits Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Masked Address Unmasked Address CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [15, 16 Mask Register bit Address Counter bit Page [+] Feedback ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C0850AV / CY7C0851V / CY7C0851AV / CY7C0852V /CY7C0852AV / CY7C0853V / CY7C0853AV incorporates an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3 ...
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... C also references C . OUT I/O 22 and I are not applicable forCY7C0853V/ CY7C0853AV because it can not be powered down by using chip enable pins. SB1 SB2 SB3 SB4 Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV DC input voltage ............................. –0 Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2000 V (JEDEC JESD22-A114-2000B) ...
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... CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 3 590 435 90% 10% < -133 -100 CY7C0853V CY7C0853V Unit CY7C0853AV CY7C0853AV Min Max Min Max – 133 – 100 MHz 7.5 – 10.0 – ns 3.0 – 4.0 – ...
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... CY7C0853V Unit CY7C0853AV Max Min Max 4.7 – 5.0 ns – 0 – ns 4.7 0 5.0 ns 4.7 – 5 – NA ...
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... Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Description Figure 7. JTAG Switching Waveform TMSS t TMSH t TDIS t TDIH t TDOX t TDOV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 167/133/100 Unit Min Max – 10 MHz 100 – – – – – – – ...
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... CD2 CKLZ = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and 1 following the next rising edge of the clock. IH with CNT/MSK = V constantly loads the address on the rising edge of the CLK CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV n n+1 n+2 t OHZ ...
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... CY7C0850AV,CY7C0851V/CY7C0851AV [31, 32] Figure 10. Bank Select Read CD2 HC CD2 SC CKHZ CD2 t CKLZ [30, 33, 34, 35, 36 n+1 n CD2 CKHZ Q n READ NO OPERATION WRITE . (B2) CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV CD2 CKHZ CKLZ CKHZ CD2 CKLZ A A n+3 n CD2 CD2 Q Q n+1 n+3 t CKLZ READ Page [+] Feedback ...
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... OHZ READ WRITE t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER with CNT/MSK = CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [37, 38, 39, 40 n+4 n CD2 CD2 Q Q n+1 n+4 READ [39] t HAD t HCN Q n+2 READ WITH COUNTER constantly loads the address on the rising edge of the CLK. ...
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... One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV A n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD t CH2 n+1 n+2 t CD2 Q n READ READ READ CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [41 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER n n+1 n+2 ...
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... DATA OUT DISABLED Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV t CH2 n n+2 WRITE READ WRITE t CH2 n+1 n OHZ n+2 t CD2 Q n READ DISABLED WRITE CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV A A n+4 n CD2 Q Q n+3 n+1 READ READ A A n+4 n+3 Q n+3 READ READ Page [+] Feedback ...
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... CL2 CH2 CLK t SAD ADS CNTEN t t SCN HCN ADDRESS COUNTER A INTERNAL n ADDRESS OE DATA OUT INCREMENT Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV t HAD A A n+1 Q n+1 NO OPERATION READ READ READBACK INCREMENT CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV n n+2 n+3 n n+3 n+2 READ READ INCREMENT INCREMENT Page [+] Feedback ...
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... No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 44. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV [42, 43, 44] Figure 19. Counter Reset CD2 t CKLZ READ WRITE READ ADDRESS 0 ADDRESS 1 CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV CD2 ...
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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [45, 46, 47, 48 n+4 n n+1 n+2 n+3 Page [+] Feedback ...
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... R_Port is Read the most recent data (written by L_Port) (t Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH CYC2 CD2 CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [49, 50, 51 violated, indeterminate data is Read out. CCS + t ) after the rising edge of R_Port's clock CYC2 CD2 ) after the rising edge of R_Port's clock. Page CCS [+] Feedback ...
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... R/W = CNTRST = MRST = HIGH 54. CNTINT is always driven. 55. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 56. The mask register assumed to have the value of 1FFFFh. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [52, 53, 54, 55, 56] 1FFFE 1FFFF Last_Loaded t t RCINT SCINT ...
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... Care,” “H” = HIGH, “L” = LOW. Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV [57, 58, 59, 60, 61 n+1 t SINT t RINT 3FFFF m+1 m [64, 65, 62, 63] Outputs CE R/W DQ – High High OUT H X High-Z CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV A A n+2 n m+3 m+4 Operation 35 Deselected Deselected Write Read Outputs disabled Page [+] Feedback ...
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... Diagram 133 CY7C0853AV-133BBC 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0853V-133BBI 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0853V-133BBXI CY7C0853V-133BBC 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch 100 CY7C0853AV-100BBC 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0853AV-100BBI 51-85114 172-Ball Grid Array ( ...
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... Ordering Code Definition 085 X Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV X XXX CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Operating Range C = Com m ercial I = Industrial free (RoHS Com pliant) Package: A=TQFP; BB=FBGA Speed in M Hz: 100/133/167 V/AV:3.3 V Depth:1=64K; 2=128K; 3=256K 0 = DP, 8=Synchronous, 5=width :x36 7 = Dual Port SRAM Com pany ID Cypress Page ...
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... Package Diagrams Figure 24. 172-Ball FBGA ( 1.25 mm) (51-85114) Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85114 *C Page [+] Feedback ...
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... Package Diagrams Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132) Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85132 *A Page [+] Feedback ...
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... TCK test clock input TDI test data input TDO test data output TQFP thin quad plastic flatpack Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...
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... Document History Page Document Title: CY7C0850AV, CY7C0851V/CY7C0851AV, CY7C0852V/CY7C0852AV, CY7C0853V/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submis- Orig. of REV. ECN NO. sion Date Change ** 127809 08/04/03 *A 210948 See ECN *B 216190 See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change ...
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... Document History Page Document Title: CY7C0850AV, CY7C0851V/CY7C0851AV, CY7C0852V/CY7C0852AV, CY7C0853V/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submis- Orig. of REV. ECN NO. sion Date Change *J 3093275 11/23/2010 Document #: 38-06070 Rev. *J CY7C0850AV,CY7C0851V/CY7C0851AV Description of Change ADMU Added new part CY7C0851AV-133BBI in the ordering information table ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06070 Rev. *J All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C0850AV,CY7C0851V/CY7C0851AV cypress.com/go/plc Revised November 23, 2010 CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...