CY7C0853V-100BBC Cypress Semiconductor Corp, CY7C0853V-100BBC Datasheet - Page 25

• Manufacturer Part Number: CY7C0853V-100BBC
• Description: IC,SYNC SRAM,256KX36,CMOS,BGA,172PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-06070 Rev. *D
Switching Waveforms
MailBox Interrupt Timing
Table 7. Read/Write and Enable Operation (Any Port)
Notes:
46. CE
47. Address “3FFFF” is the mailbox location for R_Port of a 9M device.
48. L_Port is configured for Write operation, and R_Port is configured for Read operation.
49. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
51. OE is an asynchronous input signal.
52. When CE changes state, deselection and Read happen after one cycle of latency.
CLK
L_PORT
ADDRESS
INT
CLK
R_PORT
ADDRESS
OE
R
X
X
X
H
L
L
R
0
= OE = ADS = CNTEN = LOW; CE
CLK
X
t
CH2
t
CH2
t
[46, 47, 48, 49, 50]
CYC2
Inputs
t
CYC2
(continued)
t
CE
CL2
H
X
L
L
L
t
t
3FFFF
SA
CL2
0
1
t
SA
= CNTRST = MRST = CNT/MSK = HIGH.
A
t
HA
m
t
t
HA
SINT
CE
X
H
H
H
L
1
A
n
A
R/W
[1, 8, 51, 52]
m+1
X
X
H
X
L
A
n+1
DQ
3FFFF
Outputs
High-Z
High-Z
High-Z
D
0
D
OUT
– DQ
IN
t
RINT
35
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
A
n+2
Deselected
Deselected
Write
Read
Outputs Disabled
A
m+3
Operation
A
n+3
A
m+4
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