CY7C0853V-100BBC Cypress Semiconductor Corp, CY7C0853V-100BBC Datasheet - Page 18

IC,SYNC SRAM,256KX36,CMOS,BGA,172PIN,PLASTIC

CY7C0853V-100BBC

Manufacturer Part Number
CY7C0853V-100BBC
Description
IC,SYNC SRAM,256KX36,CMOS,BGA,172PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0853V-100BBC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
9M (256K x 36)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
172-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0853V-100BBC
Manufacturer:
CY
Quantity:
19
Part Number:
CY7C0853V-100BBC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06070 Rev. *D
Switching Waveforms
Bank Select Read
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
27.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30.
31. CE
ADDRESS
ADDRESS
Read-to-Write-to-Read (OE = LOW)
DATA
DATA
ADDRESS
DATA
sheet. ADDRESS
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
DATA
ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
CE
OUT(B2)
0
OUT(B1)
0
CE
CE
CLK
R/W
= B0 – B3 = R/W = LOW; CE
OUT
= OE = B0 – B3 = LOW; CE
CE
CLK
IN
(B1)
(B1)
(B2)
(B2)
t
t
t
SW
SC
SA
t
t
t
t
SA
SC
SA
SC
(B1)
[26, 27]
= ADDRESS
A
n
A
A
0
t
0
CH2
t
CH2
t
(continued)
t
CYC2
1
t
t
1
HW
HC
HA
(B2)
= R/W = CNTRST = MRST = HIGH.
t
t
t
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
t
t
CYC2
HA
HC
HA
HC
.
t
CL2
t
CL2
[25, 28, 29, 30, 31]
A
READ
n+1
A
A
t
CD2
1
1
t
CD2
t
SW
t
Q
SC
n
Q
t
A
0
SC
n+2
t
A
CKHZ
NO OPERATION
A
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
A
A
HD
1
3
t
3
DC
t
t
CKLZ
CKHZ
WRITE
t
CD2
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
A
n+3
Q
A
A
4
4
2
t
t
t
CKHZ
CD2
CKLZ
READ
t
CKLZ
Q
3
A
n+4
Page 18 of 29
A
t
A
CD2
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
n+3
Q
4

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